Generating interface adjustment signals in a...

Details Generating interface adjustment signals in a... Generating interface adjustment signals in a...

2005-12-29

2010-06-08

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07735037

ABSTRACT:
Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

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U.S. Appl. No. 11/021,975, filed Dec. 23, 2004, Tell et al.

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