Validating integrated circuits
Validating one or more circuits using one of more grids
Validating very large network simulation results
Validation of electrical performance of an electronic...
Variable clocked scan test improvements
Variable clocked scan test improvements
Variable design rule tool
Variable detail automatic invocation of transistor level...
Variable performance ranking and modification in design for...
Variable sigma adjust methodology for static timing
Variable stage ratio buffer insertion for noise optimization...
Various methods and apparatuses to preserve a logic state...
Various methods and apparatuses to preserve a logic state...
Various methods and apparatuses to route multiple power...
VDHL/Verilog expertise and gate synthesis automation system
Vector interface to shared memory in simulating a circuit...
Vector interface to shared memory in simulating a circuit...
Vector Logic techniques for multilevel minimization
Vector logic techniques for multilevel minimization with...
Vectorless instantaneous current estimation