Five-transistor static memory cell implemental in CMOS/bulk

Flash memory cell structure

Floating body cell memory and reading and writing circuit...

Floating-body dynamic random access memory with purge line

Floating-body dynamic random access memory with purge line

Four device SRAM cell with single bitline

Four transistor static bipolar memory cell using merged transist

Fully used tub DRAM cell

Gallium arsenide addressable memory cell

Gated diode nonvolatile memory cell

Gated diode nonvolatile memory cell array

Graphics controller integrated circuit without memory interface

High density bipolar ROM having a lateral PN diode as a matrix e

High density DC stable memory cell

High density multistate SRAM and cell

High density semiconductor memory cell and memory array...

High density semiconductor memory cell and memory array...

High density semiconductor memory cell and memory array...

High density semiconductor memory cell and memory array...

High density VMOS electrically programmable ROM