High density semiconductor memory cell and memory array...

Static information storage and retrieval – Systems using particular element – Semiconductive

Reexamination Certificate

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C365S182000, C365S185180

Reexamination Certificate

active

06940751

ABSTRACT:
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, a gate dielectric of the transistor has a higher breakdown voltage near the source connected to the row wordline than its drain.

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