Gallium arsenide addressable memory cell

Details Gallium arsenide addressable memory cell Gallium arsenide addressable memory cell

1990-11-07

1991-12-31

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, 365182, G11C 1134

Patent

active

050776878

ABSTRACT:
An addressable memory cell (10) which is composed of an interrupt transistor (20) of the field-effect type whose source (S) is connected to the input terminal (I) of the cell (10) and whose gate (G) is connected to a clock (H, H) and a loop (30) which includes a first inverter (31) which is connected in series with the drain (D) of the interrupt transistor (20) and whose output is connected to the output terminal (0) of the cell (10), and a second inverter (32) which is connected in series, in the loop (30), with the first inverter (31). In accordance with the invention; the cell (10) is made of gallium arsenide and the loop (30) also includes a diode (33) which is connected in the forward direction between the output of the first inventer (31) and the input of the second inverter (32), and a resistance (34) which is connected between the output of the second inverter (32) and the input of the first inverter (31).

REFERENCES:
patent: 4469962 (1984-09-01), Snyder
patent: 4638183 (1987-01-01), Rickard et al.
patent: 4707808 (1987-11-01), Heimbigner
patent: 4777623 (1988-10-01), Shimazu et al.
E. Gonauser et al., "A Master Slice Design Concept Based on Master Cells in ESFI-SOS-CMOS Technology", Siemens Forschungs-und Entwicklungsberichte, vol. 5, No. 6, pp. 344-349, 1976.

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