High density DC stable memory cell

Details High density DC stable memory cell High density DC stable memory cell

1981-07-30

1984-02-14

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

357 23, 365182, G11C 1140

Patent

active

044313055

ABSTRACT:
An electronic data storage or memory array having DC stable memory cells which utilize the principle of a unique substrate biasing mechanism, whereby a channel region defined by resistive substrate material and formed under a controlled electrode becomes "pinched off" and, in the process, so affects the DC potential at that electrode as to maintain the pinched off condition. Consequently, the memory cell becomes established in a first DC stable state ("one" state). The principle is preferably embodied in a field effect transistor (FET), the resistive channel region being connected in a DC conductive path to a fixed resistor and a potential source. Accordingly, when appropriate signal levels representing a binary "one" are applied to word and bit lines connected to a first controlling, or gate, electrode and to a second controlling electrode, respectively, of the FET, the described pinch-off occurs, with concomitantly high resistance in the DC path, such that the potential adjacent the controlled electrode is maintained in the "one" state that was initiated by the signals on the word and bit lines. On the other hand, when signals representing a "zero" are applied to the same controlling electrodes, the resistive channel region under the controlled electrode is no longer pinched-off, whereby the memory cell becomes established in the second or "zero" DC stable state. Means for reading the stored data in the cell are integrated with the cell.

REFERENCES:
patent: 3914749 (1975-10-01), Malaviya
patent: 4070653 (1978-01-01), Rao et al.
patent: 4092735 (1978-05-01), McElroy
patent: 4122545 (1978-10-01), Lodi
patent: 4124111 (1979-02-01), McElroy
patent: 4139785 (1979-02-01), McElroy
patent: 4142112 (1979-02-01), Kroger
patent: 4352997 (1982-10-01), Raymond et al.
Mizuno et al., "Theory of Negative Resistance of Junction Field-Effect Transistors", IEEE Journal of Solid-State Circuits, 161.SC-11, No. 2, 4/76, pp. 313-317.
Baliga, "An Improved GAMBIT Device Structure," IEEE Transactions on Electron Devices, vol. ED-25, No. 12, 12/78, pp. 1411-1412.
Thomas, "The NEGIT: A surface-Control Negative Impedance Transistor," IEEE Transactions on Electron Devices, vol. ED-24, No. 8, 8/77, pp. 1070-1076.

Affiliated with

Also associated with

Rating

High density DC stable memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High density DC stable memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High density DC stable memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2372226