Five-transistor static memory cell implemental in CMOS/bulk

Details Five-transistor static memory cell implemental in CMOS/bulk Five-transistor static memory cell implemental in CMOS/bulk

1983-02-04

1985-02-12

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365189, G11C 1140

Patent

active

044995580

ABSTRACT:
A five-transistor CMOS static random-access memory cell which does not require a voltage on the address line higher than the supply voltage to effect writing, and so may be fabricated employing CMOS technology on a bulk single-crystal semiconductor substrate. The cell includes a latch comprising a complementary pair of IGFETs for actively storing one binary logic state. For storing the other binary logic state, there is only a single pull-up transistor connected to one data node and a high-impedance leakage current discharge path for the other data node. The cell also includes a pair of input/output gating transistors connected to the data nodes and operating in push-pull. Various forms of high impedance leakage current discharge path are disclosed, none of which require any increase in chip area. In one form, the high-impedance current discharge path comprises an IGFET having its gate tied to its drain terminal and having a channel extending between device regions which exist on the chip in any event for other purposes. In another form, a reverse-biased PN junction diode included in one of the gating transistors has sufficient conductivity to discharge leakage current to ground.

REFERENCES:
patent: 3493786 (1970-02-01), Ahrons et al.
patent: 3521242 (1970-07-01), Katz
patent: 3535699 (1970-10-01), Gaensslen et al.
patent: 3813653 (1974-05-01), Smith et al.
patent: 4063225 (1977-12-01), Stewart
patent: 4150441 (1979-04-01), Ando
patent: 4189782 (1980-02-01), Dingwall

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