High density semiconductor memory cell and memory array...

Details High density semiconductor memory cell and memory array... High density semiconductor memory cell and memory array...

2005-02-15

2005-02-15

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S185140, C365S185280

Reexamination Certificate

active

06856540

ABSTRACT:
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+region in the substrate underlying the gate of the transistor.

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