Mask ROM device with gate insulation film based in pad oxide fil
Masked ROM and manufacturing process therefor
Match detection circuit for cache memory apparatus
Mechanism for preventing radiation induced latch-up in CMOS inte
Memory
Memory
Memory architecture for TCCT-based memory cells
Memory arrangement with a read-out circuit for a static memory c
Memory array biasing circuit for high speed CMOS device
Memory array having 2T memory cells
Memory array having a programmable word length, and method...
Memory array having a programmable word length, and method...
Memory array of inversion controlled switches
Memory array with readout isolation
Memory array with readout isolation
Memory based on a four-transistor storage cell
Memory cell
Memory cell
Memory cell
Memory cell and array