Four device SRAM cell with single bitline

Details Four device SRAM cell with single bitline Four device SRAM cell with single bitline

1997-12-23

2000-01-04

Nelms, David

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, 36518904, G11C 1134

Patent

active

060117265

ABSTRACT:
A memory cell includes a static inverter having an input connected to a storage node. An impedance connects the storage node to a voltage supply. A first transistor, having an input connected to an output of the static inverter, connects the storage node to a write line. Lastly, a second transistor, responsive to a wordline access signal, connects the storage node to a single data bitline. The memory cell further includes a single ended four transistor CMOS SRAM cell. Additionally, a memory array is disclosed which includes a plurality of memory cells arranged to form a matrix of rows and columns, each memory cell including a single ended four transistor CMOS SRAM cell.

REFERENCES:
patent: 5805496 (1998-09-01), Batson et al.

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