Address comparison in an inteagrated circuit memory having share
Apparatus for emulating asynchronous clear in memory...
Apparatus for varying data input/output path in...
Architecture for reading information from a memory array
Balanced load memory and method of operation
Bi-directional data bus scheme with optimized read and write cha
Bi-directional data bus scheme with optimized read and write cha
Block RAM with reset
Block RAM with reset to user selected value
Block write circuit and method for wide data path memory device
Block write circuit and method for wide data path memory devices
Buffered bit-line for faster sensing and higher data rate in mem
Cells and read-circuits for high-performance register files
Column redundancy scheme for a random access memory incorporatin
Compact analog-multiplexed global sense amplifier for rams
Compact analog-multiplexed global sense amplifier for RAMS
Conditional write RAM
Connecting a short word length non-volatile memory to a long wor
Content addresable memory having programmable interconnect...
Contention-free hierarchical bit line in embedded memory and...