Bi-directional data bus scheme with optimized read and write cha

Details Bi-directional data bus scheme with optimized read and write cha Bi-directional data bus scheme with optimized read and write cha

1999-07-29

2000-10-17

Mai, Son

Static information storage and retrieval

Read/write circuit

Multiplexing

36523002, 36523004, G11C 700, G11C 800

Patent

active

061341533

ABSTRACT:
A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle. By implementing this scheme internally, a uniform read or write operating frequency is seen by the microprocessor, thereby simplifying its interface with the memory.

REFERENCES:
patent: 5568427 (1996-10-01), Takemae
patent: 5570320 (1996-10-01), Runas
patent: 5657288 (1997-08-01), Dent
patent: 5828613 (1998-10-01), Hatakeyama et al.
patent: 5831924 (1998-11-01), Nitta et al.

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