Conditional write RAM

Details Conditional write RAM Conditional write RAM

1988-08-25

1989-11-21

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Multiplexing

36523002, 365233, G11C 700

Patent

active

048827096

ABSTRACT:
To provide a means for the safe, premature, abortion of a write cycle without additional, read cycle, pipeline delays multiplexers and registers are included configured to store the address and data signals externally developed during a write cycle and to store in a RAM array the stored data at the stored address during the next write cycle. A comparator is included, configured to compare each stored address with each current address. Also included is a multiplexer configured to, during a read cycle, provide from the RAM array the currently addressed data when the current address is different than the stored address and to, during a read cycle, provide the register stored data when the current address matches the stored address.

REFERENCES:
patent: 4402067 (1983-08-01), Moss et al.

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