Balanced load memory and method of operation

Details Balanced load memory and method of operation Balanced load memory and method of operation

2002-06-28

2004-03-23

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S210130, C365S230030

Reexamination Certificate

active

06711068

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor circuits, and more specifically, to semiconductor memory circuits.
BACKGROUND OF THE INVENTION
Advances in magnetic materials have provided magnetic random access memory (MRAM) devices that are capable of high speed operations, whether in a read process or a write process. An MRAM device typically includes a plurality of memory cells arrayed on intersections of word lines and bit lines. Each cell of an MRAM device may be a type of magnetic tunnel junction (MTJ) which has magnetic layers separated by an insulating layer. Data stored in memory cells of MTJ type may be represented as a direction of magnetic vectors or dipoles in the magnetic layers, and the memory cells can hold the stored data until the direction of magnetic vectors is changed by signals externally applied to the memory cells.
Non-volatile memories, such as MRAMs, typically contain some symmetry in design between the interconnection networks that connect data signals and reference signals to a sense amplifier. Asymmetric networks negatively affect sense amplifiers used to detect states of memory cells, each having a logic state “0” or “1”, or a state of similar magnitude. For example, noise sources can be unequally coupled to an asymmetric network connecting memory cells to sense amplifiers, thereby causing delay and/or disruption of signals being sensed in the amplifiers. In a dynamic sensing system, asymmetry in an interconnection network between sense amplifiers and a memory array causes differences in load capacitance at the inputs of a sense amplifier. Such load capacitance difference in turn causes erroneous transition of the sense amplifier either from a “1” to “0” or from “0” to “1” logic values. Asymmetry in an interconnection network affects sensing speed of sense amplifiers as well. In an asymmetric interconnection network, the sensing of a valid state in a sense amplifier may also be degraded by coupling events from sources such as the substrate or neighboring metallic wires. Reohr et al. teach in U.S. Pat. No. 6,269,040 an interconnection network for connecting memory cells to two two-input sense amplifiers by using a transistor switch connected to two separate reference voltages that are connected together by a transistor switch to create a mid-level reference voltage. The transistor switch creates an asymmetry in the interconnect between the sense amplifier's two inputs, and two sense amplifiers are enabled at the same time for compensation purposes.


REFERENCES:
patent: 4713797 (1987-12-01), Morton et al.
patent: 5619449 (1997-04-01), McIntyre
patent: 6191989 (2001-02-01), Luk et al.
patent: 6269040 (2001-07-01), Reohr et al.
patent: 6552952 (2003-04-01), Pascucci

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