Block write circuit and method for wide data path memory devices

Details Block write circuit and method for wide data path memory devices Block write circuit and method for wide data path memory devices

1998-08-26

2000-01-04

Mai, Son

Static information storage and retrieval

Read/write circuit

Multiplexing

36518904, 3652385, G11C 700

Patent

active

060117273

ABSTRACT:
A block write circuit in a memory device having a wide internal data path performs block write and data masking functions. The memory device includes a plurality of data terminals adapted to receive respective data signals, and a plurality of array groups each including a plurality of arrays and each array includes a plurality of memory cells. A plurality of input/output line groups each include a plurality of input/output lines coupled to the arrays of an associated array group. The block write circuit comprises a plurality of write driver groups, each write driver group including a plurality of write driver circuits having outputs coupled to respective data lines in an associated data line group. Each write driver circuit includes an input and develops a data signal on its output responsive to a data signal applied on its input. A multiplexer circuit includes a plurality of inputs coupled to respective data terminals, and a plurality of output subgroups. Each output subgroup is associated with a respective input, and each output group includes a plurality of outputs coupled to the write driver circuits in an associated write driver group. The multiplexer circuit operates responsive to a control in a block write mode to couple each of its inputs to the outputs in the associated output subgroup. A masking circuit may also mask data from respective input/output lines responsive to masking signals.

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T. Yabe et al., "A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator" in IEEE International Solid-State Circuits Conference, 56-57 and 72-73, 1998.
R. Torrance et al., "A 33GB/s 13.4Mb Integrated Graphics Accelerator and Frame Buffer," in IEEE International Solid-State Circuits Conference, 274-275 and 340-341, 1998.
Jeffrey Dreibelbis et al., "An ASIC-Library Granular DRAM Macro with Built-In Self Test" in IEEE Internationall Solid-State Circuits Conference, 58-59 and 74-75, 1998.

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