Contention-free hierarchical bit line in embedded memory and...

Static information storage and retrieval – Read/write circuit – Multiplexing

Reexamination Certificate

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Details

C365S063000, C365S230020, C365S230030, C365S230060

Reexamination Certificate

active

07440335

ABSTRACT:
A memory includes a plurality of lower level bit lines, a higher level bit line, and bit line driving circuitry. The bit line driving circuitry includes a plurality of bit line inputs, each bit line input coupled to a corresponding one of the plurality of lower level bit lines. The bit line driving circuitry further includes a first select input to receive a first select value, a second select input to receive a second select value, and an output configured to drive a select one of first bit value or a second bit value at the third bit line based on the first select value and the second select value and a bit value of at least one of the plurality of lower level bit lines.

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