Block write circuit and method for wide data path memory device

Details Block write circuit and method for wide data path memory device Block write circuit and method for wide data path memory device

2001-12-20

2003-05-06

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S189040, C365S238500

Reissue Patent

active

RE038109

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memories, and more specifically to a method and circuit for performing a block write data transfer in a memory device having a wide internal data path.
BACKGROUND OF THE INVENTION
A computer system typically includes a video system that displays information for a computer user. In a typical video system, a video controller accesses data stored in video memory and drives a display unit, such as a cathode ray tube, to display the stored information, as understood by one skilled in the art. The video memory typically includes specialized dynamic random access memories (“DRAM”), such as a synchronous graphics DRAM (“SGRAM”), which include special functions that enable the video controller to more efficiently access stored video data and drive the display unit. Such special functions typically include bit-masking, byte-masking, and block write functions. In bit-masking, selected bits of write data applied on a data bus of the SGRAM are masked from corresponding addressed memory cells so the data stored in those cells is not overwritten. Byte-masking is analogous to bit-masking except that bytes of write data applied on the data bus are selectively masked from eight corresponding memory cells. The block write function enables the SGRAM to transfer a single bit of data to a group or block of memory cells, which reduces the time it takes to transfer the same data to a large number of memory cells. A typical application of the block write function is writing data corresponding to a desired background color for a video screen to a plurality of memory cells in the SCRAM.
FIG. 1
is a functional block diagram of a portion of a conventional SGRAM
100
including a conventional block write circuit
102
coupled to a memory-cell arrayed
104
including a plurality of memory cells (not shown) arranged in rows and columns. A block
106
of memory cells in the array
104
is shown, and corresponds to a group of eight memory cells in an activated row in the array. A number of digit lines DL
0
-DL
7
are shown coupled to respective memory cells in the block
106
. One skilled in the art will realize the depiction of the array
104
has been simplified for ease of explanation, and that components such as sense amplifiers and complementary signal lines have been omitted for the sake of brevity.
The block write circuit
102
includes a column mask decoder
108
receiving a number of column mask bits CM
0
-CM
7
stored in a column mask register
110
. The column mask bits CM
0
-CM
7
correspond to data placed on respective data terminals DQ
0
-DQ
7
coincident with a block write command applied to the SGRAM
100
, as understood by one skilled in the art. In response to the column mask bits CM
0
-CM
7
, the column mask decoder
108
activates a number of column select signals CSEL
0
-CSEL
7
. When one of the column mask bits CM
0
-CM
7
is set, the column mask decoder
108
deactivates the corresponding column select signal CSEL
0
-CSEL
7
, and when one of the mask bits CM
0
-CM
7
is cleared, the column mask circuit
108
activates the corresponding column select signal CSEL
0
-CSEL
7
. A number of input/output transistors
112
a-h are coupled between the digit lines DL
0
-DL
7
, respectively, and an input/output or input/output line I/O
1
. Each of the transistors
112
a-h receives on its gate a respective one of the column select signals CSEL
0
-CSEL
7
. The transistors
112
a-h each turn ON when the applied one of the column select signals CSEL
0
-CSEL
7
is active, and thereby couples the input/output line I/O
1
to the corresponding digit lines DL
0
-DL
7
. When any of the column select signals CSEL
0
-CSEL
7
is inactive, the corresponding transistors
112
a-h turn OFF, isolating the corresponding digit lines DL
0
-DL
7
from the input/output line I/O
1
.
A write driver
114
receives on its input either a color bit CR
0
or a write data bit applied on the data terminal DQ
0
, and applies the data on its input to the input/output line I/O
1
in response to a masking signal {overscore (M)} received on an enable input. An AND gate
116
develops the mask signal {overscore (M)} in response to a byte-mask signal DQM
0
applied on a first input and a mask bit MR
0
applied on a second input. When the mask bit MR
0
is set low or the byte-mask signal is active high, the AND gate
116
drives the mask signal {overscore (M)} active low, and when the mask bit MR
0
is cleared high and the byte-mask signal DQM
0
is inactive low, the AND gate
116
drives the mask signal {overscore (M)} inactive high. In operation during a standard write operation, conventional address decode circuitry (not shown in
FIG. 1
) decodes address signals applied to the SGRAM
100
and activates a corresponding memory cell in the array
104
, as understood by one skilled in the art. The write driver
114
then transfers data applied on the terminal DQ
0
onto the input/output line I/O
1
when the mask signal {overscore (M)} is inactive high, and places its output in a high-impedance state to isolate or “mask” this data from the input/output line I/O
1
when the mask signal {overscore (M)} is active low.
In operation during a block write data transfer, the block write circuit
102
transfers the color bit CR
0
to selected ones of the memory cells in the block
106
, as will now be described in more detail. During a block write, the address decode circuitry once again decodes address signals applied to the SGRAM
100
, and activates corresponding memory cells in the array
104
, as understood by one skilled in the art. If either the mask bit MR
0
is set or the byte-mask signal DQM
0
is active high, the write driver
114
places its output in a high impedance state, masking the color bit CR
0
from the memory cells in the block
106
independent of the state of the column select signals CSEL
0
-CSEL
7
. In this situation, the data stored in the block
106
is not altered during the block write operation. When the mask bit MR
0
is cleared and the byte-mask signal DQM
0
is inactive low, the write driver
114
places the color bit CR
0
on the input/output line I/O
1
, and the column mask decoder
108
activates selected ones of the column select signals CSEL
0
-CSEL
7
in response to the column mask bits CM
0
-CM
7
. In response to the column select signals CSEL
0
-CSEL
7
, selected ones of the transistors
112
a-h turn ON, coupling the corresponding digit lines DL
0
-DL
7
to the input/output line I/O
1
. The color bit CR
0
is then transferred through the activated ones of the transistors
112
a-h and over the corresponding digit lines DL
0
-DL
7
to respective memory cells in the block
106
. If any of the column mask bits CM
0
-CM
7
is set, the corresponding one of the column select signals CSEL
0
-CSEL
7
is deactivated, turning off the associated one of the transistors
112
a-h and thereby masking the color bit CR
0
from the corresponding memory cell in the block
106
. For example, when the column mask bit CR
6
is set, the column select signal CSEL
6
is deactivated, turning OFF the transistor
112
g and thereby masking the color bit CR
0
from the memory cell in the block
106
coupled to the digit line DL
6
. In this way, the column mask decoder
108
masks the color bit CR
0
from respective cells within the block
18
, which is known as “column masking.”
From this description, it is seen that during a block write, several of the transistors
112
a-h are typically simultaneously activated, coupling several of the digit lines DL
0
-DL
7
to the input/output line I/O
1
. In fact, when none of the column mask bits CM
0
-CM
7
is set, all of the transistors
112
a-h are turned ON, coupling all of the digit lines DL
0
-DL
7
to the input/output line I/O
1
. As more digit lines DL
0
-DL
7
are coupled to the input/output line I/O
1
, the load presented by the input/output line I/O
1
increases, and this increased load must be driven by the write driver
114
. The load presented by the input/output line I/O
1
increases because each of the digit li

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