Static information storage and retrieval – Read/write circuit – Multiplexing
Reexamination Certificate
2001-12-28
2003-03-04
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Multiplexing
C365S225700
Reexamination Certificate
active
06529419
ABSTRACT:
RELATED APPLICATION
The present application claims the benefit of Korean Patent Application No. 87288/2000 filed Dec. 30, 2000, under 35 U.S.C. §119, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an apparatus for varying a data input/output path in a semiconductor memory device having
9
data input/output lines (hereinafter abbreviated as X
9
) including a parity bit line, which allows an X
9
construction of the semiconductor memory device to change into a construction having
8
data input/output lines (hereinafter abbreviated as X
8
) including no parity bit line, by varying an input/output path of data when memory cells corresponding to one of the input/output lines are degraded.
2. Discussion of the Related Art
In a general DRAM semiconductor memory device, a signal, which is outputted from a memory cell array and amplified by a bit line sense amplifier (BLSA), is transferred to a data bus line from a bit line under control of a column selector. The signal loaded on the data bus line is amplified by a data bus sense amplifier (DBSA) and then outputted through an output line and a pad to an appropriate location. An external signal inputted through the pad is loaded on the data bus through a write data driver and then amplified by the BLSA so as to be written in the corresponding memory cell.
A general semiconductor device having the X
9
construction, as shown in
FIG. 1A
, includes DBSAs
10
and nine (
9
) data input/output parts I/
00
to I/
08
each of which includes an input/output pad
12
. Input/output (write and read) operations of the device, as described above, are independently carried out by the respective data input/output parts I/
00
to I/
08
.
Another general semiconductor device having the X
8
construction, as shown in
FIG. 1B
, includes DBSAs
14
and eight (
8
) data input/output parts I/
00
to I/
07
each of which includes an input/output pad
16
. Input/output (write and read) operations of the device, as described above, are independently carried out by the respective data input/output parts I/
00
to I/
07
.
Unfortunately, in the semiconductor device having the X
9
or X
8
construction according to the related art, it is difficult to change the X
9
construction of a product into the X
8
construction because data are inputted/outputted only through the corresponding data input/output parts. Therefore, the X
9
-configured semiconductor devices according to the related art cannot be used if one of the memory cells corresponding to the input/output parts is degraded in the X
9
construction, whereby the yield of the device is reduced and its product cost is increased.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an apparatus for varying a data input/output path in a semiconductor memory device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an apparatus for varying a data input/output path in a semiconductor memory device to allow a X
9
-configured product to be transformed into a X
8
-configured product, whereby yield of the device is improved and the product cost is reduced.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, an apparatus for varying a data input/output path in a semiconductor memory device according to an embodiment of the present invention, includes a plurality of DBSAs amplifying a signal loaded on a data bus after being amplified by a BLSA, a plurality of fuse circuits producing signals of specific levels respectively in accordance with whether or not fuses are cut, a plurality of input multiplexers each of which selects an external signal inputted through a corresponding pad or another external signal inputted through a pad next to the corresponding pad in accordance with the output signals of the fuse circuits and applies the selected signal to a write driver, and a plurality of data input/output parts including respectively a plurality of output multiplexers each of which selects a signal outputted from a corresponding one of the DBSAs or another one next to the corresponding DBSA in accordance with the output signal of the fuse circuits and outputs the selected signal to outside through a corresponding one of the pads.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5301153 (1994-04-01), Johnson
patent: 5812466 (1998-09-01), Lee et al.
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Lam David
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