Static information storage and retrieval – Read/write circuit – Multiplexing
Reexamination Certificate
2000-07-24
2001-08-28
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Multiplexing
C365S189050, C365S189080
Reexamination Certificate
active
06282127
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits, more particularly to field programmable logic devices having blocks of RAM.
BACKGROUND
FIG. 1
shows a RAM used as a ROM and configured as a finite state machine. Some of the finite state machine (FSM) input wires carry input signals and some carry feedback signals to tell what state the machine is in. Together, these signals form the address of a memory cell in the ROM. Data output from the addressed word of the ROM goes on data-out wires, some of which are state wires that feed back to the address input ports, and some of which form the FSM output. In a state machine some of the address bits are controlled by output data fed back from the block RAM and other address bits are provided externally.
FIG. 2
shows an example state machine that can be implemented by the ROM structure of FIG.
1
. This state machine moves up one state or remains in the highest state in response to a data value of 01. It moves down one state or remains in the lowest state in response to a data value of 00. And it resets to state 00 in response to a data value of 10 or 11. In other words, the first bit serves as a reset signal.
FIG. 3
shows the addresses and data values to be stored in the ROM structure of
FIG. 1
for implementing this state machine. Sixteen memory locations are required in order to get the fast reset to state 00 required by the state machine of FIG.
2
.
It would be preferable to use fewer memory locations to implement such a simple state machine.
SUMMARY OF THE INVENTION
According to the invention, a RAM includes a circuit for causing the RAM to provide all 0's on the output when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the RAM to be 0 (or 1 in another embodiment). This is useful, for one example, when the RAM is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine feeds back the state of 0 to the address inputs of the RAM that receive state feedback data, regardless of the data actually in those locations. The circuit of the invention is also useful in any case where the user wishes to mask the RAM output data without using additional gating circuitry that may hurt performance.
In another embodiment of the invention, the RAM includes a circuit for causing the RAM to provide a value regardless of the RAM contents when a set/reset signal is active. The reset value is programmable by the user. Additionally, the circuit has the ability to capture the value output by the RAM and restore that value when a Restore signal is active.
REFERENCES:
patent: 5421000 (1995-05-01), Fortino et al.
patent: 5835406 (1998-11-01), Chevallier et al.
patent: 5844851 (1998-12-01), Pascusi et al.
patent: 5923594 (1999-07-01), Voshell
patent: 5923595 (1999-07-01), Kim
Bauer Trevor J.
Pang Raymond C.
Young Steven P.
Brown, Esq. Scott R.
Dinh Son T.
Xilinx , Inc.
Young Edel M.
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