Architecture for reading information from a memory array

Details Architecture for reading information from a memory array Architecture for reading information from a memory array

1994-05-09

1995-07-04

Callahan, Timothy P.

Static information storage and retrieval

Read/write circuit

Multiplexing

365201, G11C 700

Patent

active

054306779

ABSTRACT:
In a memory array having a plurality of rows and columns of memory devices for storing binary conditions, apparatus for selecting particular memory devices, a sense amplifier for transferring indications of the conditions of selected memory devices, and apparatus for generating signals indicative of conditions other than the state of the memory devices, the improvement including a multiplexor, the multiplexor being arranged to accept as input the output of the sense amplifier and the signals indicative of conditions other than the state of the memory devices, the multiplexor and the apparatus for generating signals indicative of conditions other than the state of the memory devices being positioned in a manner that parasitic capacitance affecting the input to the sense amplifier is not created. The output of the sense amplifier may also be connected to other internal circuits so that the memory array may be accessed while bringing other signals to the output pins.

REFERENCES:
patent: 4636987 (1987-01-01), Norwood et al.
patent: 4685088 (1987-08-01), Iannucci
patent: 4691300 (1987-09-01), Pelley, III et al.
patent: 4807191 (1989-02-01), Flannagan
patent: 4951252 (1990-08-01), White et al.
patent: 5046047 (1991-09-01), Cliff et al.
patent: 5083295 (1992-01-01), Lammerts et al.
patent: 5185720 (1993-02-01), Vaillancourt et al.

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