Block RAM with reset

Details Block RAM with reset Block RAM with reset

1999-02-03

2000-08-08

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Multiplexing

36518908, 36523002, G11C 700

Patent

active

061011320

ABSTRACT:
A RAM block includes a circuit for causing the RAM to provide all 0's on the output when a Reset signal is active. The Reset signal does not change the RAM contents but causes all outputs of the block RAM to be 0. This is useful when the RAM block is configured as a state machine. Thus, in an FPGA or other programmable device, an application can start the state machine in a known state with all address bits equal to 0 and can reset the state machine to this startup state. When the reset signal is active, the state machine feeds back the state of 0 to the address inputs of the RAM block that receive state feedback data, regardless of the data actually in those locations.

REFERENCES:
patent: 5421000 (1995-05-01), Fortino et al.
patent: 5835406 (1998-11-01), Chevallier et al.
patent: 5844851 (1998-12-01), Pascusi et al.
patent: 5923594 (1999-07-01), Voshell
patent: 5923595 (1999-07-01), Kim

Affiliated with

Also associated with

Rating

Block RAM with reset does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Block RAM with reset, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Block RAM with reset will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1156580