Buffered bit-line for faster sensing and higher data rate in mem

Details Buffered bit-line for faster sensing and higher data rate in mem Buffered bit-line for faster sensing and higher data rate in mem

1999-01-15

2000-10-24

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Multiplexing

36523003, 365190, G11C 700

Patent

active

061377309

ABSTRACT:
A semiconductor integrated circuit device includes a plurality of memory cells subdivided into array blocks each including M cell rows and N cell columns. The array blocks are arranged in array block rows and array block columns. Each cell of each cell row of each array block is coupled to an associated one of M word lines. Each cell of each cell column is selectively coupled to develop a data signal transmitted between an associated bit line pair including a primary bit line and a complementary bit line. A row decoder is coupled to provide a corresponding row address signal to each of the M word lines for addressing the cell rows. Each array block column includes: a plurality of column multiplexers each including N multiplexer input ports connected to receive one of the data signals from one of the bit line pairs of an associated one of the array blocks, and a multiplexer output port providing the data signals from selected ones of the N multiplexer input ports; a plurality of intermediate sense amplifiers each having an amplifier input port connected to receive the data signals from a corresponding one of the multiplexer output ports, and an amplifier output port providing pre-amplified data signals; a plurality of column demultiplexers each including an input port connected to receive a pre-amplified data signal, and a plurality of demultiplexer output ports each connected to one of the bit line pairs of a corresponding one of the array blocks.

REFERENCES:
patent: 5506815 (1996-04-01), Hsieh et al.
patent: 5519655 (1996-05-01), Greenberg

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