LandOfFree - US Patents - Listing for Semiconductor device manufacturing: process,Making field effect device having pair of active regions...

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Vertical gated access transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Vertical internally-connected trench cell (V-ICTC) and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical memory cell and manufacturing method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical memory device and method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical MOS transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical MOS transistor and method of manufacturing the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical MOS transistor and method therefor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical MOS transistor device with asymmetrical source and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical MOSFET

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical MOSFET and method of manufacturing thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical MOSFET with asymmetric gate structure

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical nano-size transistor using carbon nanotubes and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Vertical nano-size transistor using carbon nanotubes and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Vertical nitride read-only memory cell and method for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical NPN transistor for 0.35 micrometer node CMOS logic tech

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical NROM NAND flash memory array

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical PNP transistor and method of making same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical power component manufacturing method

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

Reexamination Certificate

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Vertical replacement-gate junction field-effect transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Vertical replacement-gate silicon-on-insulator transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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