Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2000-11-02
2003-04-22
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S221000, C438S294000
Reexamination Certificate
active
06551868
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power components of vertical type capable of withstanding high voltages.
2. Discussion of the Related Art
FIG. 1
is a very simplified cross-section view illustrating the general structure of a conventional power component. This component is formed in a large silicon wafer and is surrounded at its external periphery with an isolating wall of a conductivity type opposite to that of the substrate. This isolating wall is intended to separate the component from other components on the same chip, or for creating an electrically inactive protection area at the border of a chip, where a cutting is performed with respect to a neighboring chip. More specifically, referring to
FIG. 1
, starting from an N-type substrate, a first manufacturing operation consists of forming from, the upper and lower surfaces of this substrate, deep diffusion regions
2
and
3
that join to form the isolating wall.
For practical reasons, the wafers cannot have thicknesses under 200 &mgr;m. Under this threshold, they would be likely to break too easily in handling associated with the manufacturing process. Thus, each of deep diffusions
2
and
3
must penetrate into the wafer by some hundred &mgr;m, for example, 125 &mgr;m for a wafer of a thickness from 210 to 240 &mgr;m, to ascertain that a continuous wall, sufficiently doped at the level of its median portion, is formed. This requires very long diffusions at high temperatures, for example 300 hours at 1280° C. Clearly, this operation must be performed on a silicon wafer before any other wafer doping operation. Otherwise, during this long thermal processing time, the implantations previously performed in the substrate would diffuse too deeply.
After forming the isolating walls, doped regions intended to form the desired vertical component, for example, as shown in
FIG. 1
, a thyristor, are formed. For this purpose, a P-type region
4
corresponding to the thyristor anode may be formed on the entire lower substrate surface, simultaneously to a P-type region
5
corresponding to the cathode gate region of this thyristor, on a portion of the upper substrate surface. Then, on the upper surface side, an N
+
diffusion is performed to form in region
5
a cathode region
6
and possibly, between region
5
and isolating wall
2
, a peripheral channel stop ring
7
.
As seen previously, the total thickness of the wafer is determined by manufacturing considerations, which are essentially mechanical. Further, the characteristics of P-type regions
4
and
5
are determined by the desired electric characteristics of the thyristor, which determine the doping level and the diffusion depth. Indeed, it is, for example, desired to have a sufficiently steep doping front between each of regions
4
and
5
and substrate
1
to improve the characteristics of the corresponding junctions, and especially to obtain a good injection characteristic of the PNP transistor at the level of the junction between substrate
1
and region
4
.
Thus, in the case of the shown thyristor, if each of diffusions
4
and
5
has a depth on the order of 40 &mgr;m, and if the wafer has a 210-&mgr;m thickness, there will remain between P-N junctions
5
-
1
and
4
-
1
an area of substrate
1
having a 130-&mgr;m thickness. As is well known, this area of the substrate provides the off-state breakdown voltage characteristics to the power device. This area must thus be sufficiently thick. However, an excessive thickness of this area results in an increase of on-state losses of the power device. If a power device having a breakdown voltage on the order of 400 volts is desired to be obtained, it would be sufficient for the thickness of the region of substrate
1
to be on the order of 80 &mgr;m whereas, with the described manufacturing method, a thickness on the order of 130 &mgr;m is inevitably provided. No simple way of solving this problem is currently known. Indeed, increasing, for example, the thickness of layer
4
has the consequence that the junction profile of this layer risks not fulfilling the desired electric conditions.
More generally, the same problem is raised with any power device to be surrounded with an isolating wall, the rear surface of which is of a doping type opposite to that of a breakdown voltage substrate, for example a power transistor or an IGBT transistor.
SUMMARY OF THE INVENTION
Thus, an object of the present invention is to provide a novel method of manufacturing power components intended for or optimize the thickness of the most lightly doped breakdown voltage layer.
The present invention also aims at a component obtained by the described method.
To achieve these and other objects, the present invention provides a method for manufacturing a vertical power component on a silicon wafer, including the steps of growing a lightly-doped epitaxial layer of a second conductivity type on the upper surface of a heavily-doped substrate of a first conductivity type, the epitaxial layer having a thickness adapted to withstanding the maximum voltage likely to be applied to the power component during its operation; and delimiting in the wafer an area corresponding to at least one power component by an isolating wall formed by forming a trench through the epitaxial layer and diffusing from this trench a dopant of the first conductivity type of high doping level.
According to an embodiment of the present invention, the trench is formed of neighboring openings sufficiently close to one another for the areas resulting from the diffusion of the dopant of the first conductivity type of high doping level to join.
According to an embodiment of the present invention, the trench is filled with heavily-doped polysilicon.
According to an embodiment of the present invention, parallel isolating walls are formed on either side of each cutting area of the chips of the same wafer.
The present invention also provides a vertical power component formed on a silicon wafer including an epitaxial layer of the second conductivity type of low doping level formed on a substrate of the first conductivity type of high doping level, in which an isolating wall at the periphery of the power component is formed from a trench or holes formed through the epitaxial layer and from diffused regions extending from said trench or said holes.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 4829017 (1989-05-01), Malhi
patent: 4889492 (1989-12-01), Barden et al.
patent: 5049521 (1991-09-01), Belanger et al.
patent: 5497026 (1996-03-01), Vogelzang
patent: 5688702 (1997-11-01), Nakagawa et al.
patent: 5998822 (1999-12-01), Wada
patent: 2001/0011717 (2001-08-01), Mathieu
patent: 2002/0014678 (2002-02-01), Erratico
patent: A-0 236 811 (1987-09-01), None
patent: A-0 597 266 (1994-05-01), None
patent: A-2 675 310 (1992-10-01), None
French Search Report from French Patent Application 99 14012, filed Nov. 3, 1999.
Patent Abstracts of Japan, vol. 006, No. 077 (E-106), May 14, 1982 & JP 57 017145 A (Fujitsu Ltd.).
Auriel Gérard
Cornibert Laurent
Le Vu A.
Morris James H.
Smith Brad
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
LandOfFree
Vertical power component manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertical power component manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical power component manufacturing method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3026530