Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-30
2003-05-20
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S387000, C438S391000
Reexamination Certificate
active
06566190
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and methods of manufacturing the same, and more particularly, to deep trench dynamic random access memory (DT DRAM) cells having a substantially lower cell capacitance and method of manufacturing the same.
2. Discussion of Related Art
Dynamic random access memory (DRAM) requires refreshing to maintain its stored charge. A DRAM cell operates by storing a charge on its capacitor for a logic 1 and not storing any charge for a logic 0. Stable circuit operation is achieved by having a large enough capacitor and a charge transfer device that retains the stored charge such that the signal-to-noise ratio is sufficient.
A modern deep trench DRAM (DT DRAM) device almost exclusively relies on a buried strap (BS) to electrically connect source/drain (SID) junctions to storage node electrodes. Since the BS is formed in a Si body via a p-n junction, it is leaky. This leaky connection necessitates that a high capacitance level (i.e.,>40 fF/cell) be maintained in order to amplify its signal to overcome RC noise. Typically, this high capacitance requirement has been satisfied through the use of deep trench capacitors that minimize required surface space while maintaining the charge storage capacity of the capacitor.
However, present reliance on BS technology is not satisfactory in many instances and has driven the search for new processes and materials, e.g., high-k dielectric node, DT surface enhancement, low resistance metallic fill of DT, etc. These approaches are not only expensive but are also relatively immature, and many have yet to be tried in a production environment. Further, as DRAMs are scaled down to meet higher density requirements, leakage increases make the issue of retention of charge more significant.
The minimum feature size, F, of a DRAM device is commonly referred to in the art as the ground rule (GR). To determine the area of a DRAM cell, the X-direction cell width is multiplied by the Y-direction cell width, where both dimensions are represented in terms of squared GR units, i.e., in multiples of F
2
. In a conventional DRAM design, at least one rowline, a space between rowlines, a capacitor and a contact to device must be created within the X-direction for a total width of 4F and at least one digit line and a space between digit lines must be created in the Y-direction, yielding a minimum total cell area of 8F
2
. As the size of DRAM arrays is decreased while the density of the integrated circuits within them is correspondingly increased, new trench gates and processes to form them will be required.
As DRAM device design density requirements shrink below GR<110 nm, DT and its collar formation becomes extremely difficult. The generally held view is that at GR<100 nm, a vertical transistor is required to overcome a short-channel effect (SCE), and such a vertical transistor will enable a Sub-8F
2
area DT DRAM layout, in principle. However, the actual manufacturing of fully functional Sub-8F
2
area DRAM devices has to date been impeded by excess BS out-diffusion.
Device development has also been trending towards a fully depleted device design that improves speed and incorporates latch-up immunity. Such devices can be realized by a thin silicon-on-insulator (SOI) structure, since SOI devices are completely free of latch-up. A large amount of successful research effort has been dedicated to the formation of robust SOI applications. However, heretofore, there has not been much success in the formation of a vertical SOI structure due to the complexity of process integration.
SUMMARY OF THE INVENTION
Thus, there is a need for a fully depleted vertical cell that minimizes BS out-diffusion. The present invention discloses a fully depleted vertical cell with a direct connection between storage nodes and transistors without BS out-diffusion. The vertical-internally connected trench cell (V-ICTC) of the present invention overcomes this difficulty by naturally forming a collar during the transistor formation process so that the strap is connected inside the collar without any direct link to the Si substrate. BS out-diffusion is thereby avoided.
The present invention also provides a process integration scheme for fabricating DRAM devices that employs an internally-connected strap (ICS) structure to replace a conventional buried strap (BS) structure. The ICS directly connects a memory storage node to a source/drain (S/D) junction region of a transistor directly without forming a p-n junction in a Si body, thereby eliminating a p-n junction that is intrinsically leaky.
The ICS of the present invention enables deep trench (DT) memory cells to operate at a substantially lower cell capacitance than that required for a conventional BEST (Buried Strap Trench) cell without causing any negative impact on device performance for its low leakage characteristics. The lower cell capacitance requirement of the device of the present invention extends the feasibility of current DT capacitor manufacturing at technology without reliance on relatively untested new materials and processing methods, such as high-k dielectric node, surface enhancement, low resistance metal fill, etc., and their implementation.
The V-ICTC fabrication method of the present invention employs internal thermal oxidation (ITO), which forms embedded oxide isolation layers under an Si substrate by an angled implantation of oxygen ions followed by a thermal anneal, forming a virtual collar oxide layer. This method forms a very thin Si layer on top of a DT cell and, at the same time, forms an isolated layer in place of a conventional collar.
The SOI by ITO makes the structure in such a manner that the device may be fully depleted. The fully depleted V-ICTC device of the present invention makes it possible to design a Sub-8F
2
cell layout employing controlled strap formation. The V-ICTC device of the present invention is a high performance device due to its completely isolated, thin channel layer without leakage, thus improving device speed while lowering operating power requirements.
See K. Kawamura, et al.,
Gate Oxide Integrity on ITOX
-
SIMOX Substrates and Influence on Test Device Geometry on Characterization,
IEEE Transactions on Electron Devices, Vol. 48, No. 2, February 2001, pp 307-315 and 5 Lee et al., Plasma Immersion Ion Implantation as an Alternative Deep Trench Buried Plate Doping Technology, ITT 2000, incorporated by reference herein, for a discussion of theoretical background.
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C.J. Radens et al., A 0.135 Micron 2 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM. IEEE 2000, pp. 80-81.*
K. Kawamura, et al., “Gate Oxide Integrity on ITOX-SIMOX Substrates and Influence of Test Device Geometry on Characterization”, IEEE Transactions on Electron Devices, vol. 48, No. 2, Feb. 2001, pp. 307-315.
K. Lee, et al., “Plasma Immersion Ion Implantation as an Alternative Deep Trench Buried-Plate Doping Technology”, ITT 2000.
Lee Brian S.
Walsh John
Duy Mai Anh
Fahmy Wael
Promos Technologies Inc.
Stevens Davis Miller & Mosher LLP
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