Vertical MOSFET and method of manufacturing thereof

Details Vertical MOSFET and method of manufacturing thereof Vertical MOSFET and method of manufacturing thereof

1997-02-04

2000-10-17

Booth, Richarad

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438589, H01L 21336

Patent

active

06133099&

ABSTRACT:
A vertical MOSFET of the present invention comprises a semiconductor wafer having a groove selectively etching in the semiconductor wafer to have substantially vertical side walls. The groove is oxidized using local oxidation of silicon (LOCOS) at 1100.degree. C. or greater to form a LOCOS film on the semiconductor wafer in the groove so that a whole side surface of said semiconductor wafer exposed by the groove is substantially vertical and essentially flat. The LOCOS film in the groove is removed and a thermal insulating film on the semiconductor wafer in the groove. Then a gate electrode made of a conductive film is formed on the thermal insulating film. An interlayer insulating film is formed on the gate electrode and a source electrode is formed in ohmic contact with a source region and a base region. A drain electrode is connected to the opposite side of the semiconductor wafer. As a result, the vertical MOSFET of the present invention has improved on-state resistance, reduced parasitic capacitance and higher breakdown voltage.

REFERENCES:
patent: 5151381 (1992-09-01), Liu et al.
patent: 5399515 (1995-03-01), Davis et al.
patent: 5460985 (1995-10-01), Tokura et al.
patent: 5672524 (1997-09-01), Liu et al.
patent: 5763310 (1998-06-01), Gardner
patent: 5858866 (1999-01-01), Berry et al.
Tokura et al., "The DMOS Consisting of Channel Region Defined by LOCOS (LOCOS-DMOS): A New Process/ . . . MOSFET", 5th International Symposium on Power Semiconductor Devices and ICs, 1993, pp. 135-140.

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