Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-23
2003-01-28
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S416000, C438S589000
Reexamination Certificate
active
06511885
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a vertical MOS transistor in which a high frequency characteristic is improved as compared with the prior art vertical MOS transistor by lowering feedback capacitance, and a method of manufacturing the same.
2. Description of the Related Art
FIG. 2
is a schematic sectional view showing an example of a conventional vertical MOS transistor.
This vertical MOS transistor includes an n+ semiconductor substrate
1
. A drain electrode
1
a
is connected to the n+ semiconductor substrate
1
. An n− epitaxial growth layer
2
is formed on the n+ semiconductor substrate
1
. A p− body region
3
is formed on the n+ epitaxial growth layer
2
. Further, a trench
4
is formed so as to reach the inside of the n− epitaxial growth layer
2
through the p− body region
3
, and a gate oxide film
5
is formed along the wall surface of the trench
4
. A gate
6
of polycrystalline silicon is filled in the trench
4
so as to be surrounded by the gate oxide film
5
. A gate electrode
6
a
is connected to the gate
6
. An n+ source layer
7
is formed on the surface of the p− body region
3
and at the periphery of the trench
4
. A source electrode
7
a
is connected to the n+ source layer
7
. A p+diffusion region
8
is formed on the surface of the p− body region
3
and at a region separate from the n+ source layer
7
. A body electrode
8
a
is connected to the p+ diffusion region
8
.
In this vertical MOS transistor, when a gate voltage is applied through the gate electrode
6
a
, a channel is formed along the trench
4
in the p− body region
3
, and an electron current flows from the n+ source layer
7
to the n− epitaxial growth layer
2
.
However, the conventional vertical MOS transistor of
FIG. 2
has various problems, as follows:
In the vertical MOS transistor of
FIG. 2
, a large area of overlap exists between the gate
6
and the n+ semiconductor substrate
1
serving as a drain through the gate oxide film
5
, and a large capacitance is formed between the gate
6
and the n+ semiconductor substrate
1
. Thus, in the case where the conventional vertical MOS transistor is used as, for example, a source grounded circuit, since a reverse phase output voltage to an input gate voltage is applied through the feedback capacitance, there has been a problem in that the high frequency characteristic of voltage amplification is inhibited. In order to solve this problem, there is generally taken a countermeasure to lessen the influence of the feedback capacitance by making a cascade connection of a gate grounded circuit to the source grounded circuit. However, when the gate grounded circuit is added, the number of parts increases and the circuit becomes more complicated.
Further, the vertical MOS transistor of
FIG. 2
has a problem as shown in
FIGS. 3A and 3B
.
FIGS. 3A and 3B
are structural views of a case where a metal contact pattern M is provided in the vertical MOS transistor of
FIG. 2
,
FIG. 3A
is a plan view and
FIG. 3B
is a sectional view taken along line A-A′ of FIG.
3
A.
As shown in
FIG. 3B
, in the case where the n+ source layer
7
is connected to the p+ diffusion region
8
through the metal contact pattern M, it is necessary that the contact pattern M is formed to be larger than the p+ diffusion region
8
, and further, it is necessary that the contact pattern is formed in view of the margin including a positional deviation at patterning as well. Thus, as shown in
FIG. 3A
, there has been a problem that a lattice pattern becomes inevitably large, and miniaturization is difficult.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, according to the present invention, a vertical MOS transistor includes a semiconductor substrate of a first conductivity type, a first epitaxial growth layer of a second conductivity type formed on the semiconductor substrate, a second epitaxial growth layer of the first conductivity type formed on the first epitaxial growth layer, a trench formed so as to reach the inside of the semiconductor substrate through the second epitaxial growth layer and the first epitaxial growth layer, a gate oxide film formed along the surface of the second epitaxial growth layer and the wall surface of the trench, a gate which is filled in the trench so as to be surrounded by the gate oxide film and which has its upper portion coincident with an upper portion of the first epitaxial growth layer, a drain layer of the first conductivity type formed on the surface of the second epitaxial growth layer and at the periphery of the trench, a gate electrode connected to the gate, a drain electrode connected to the drain layer, and a source electrode connected to the semiconductor substrate.
By this, a positional relation between the drain layer and the source layer with respect to the gate comes to have an opposite structure to the prior art, and an overlapping area between the gate and the drain layer through the gate oxide film becomes small. Thus, the capacitance formed between the gate and the drain becomes smaller than the prior art, and the feedback capacitance becomes smaller than the prior art.
A method of manufacturing a vertical MOS transistor comprises a first epitaxial growth layer formation step of forming a first epitaxial growth layer of a second conductivity type on a semiconductor substrate of a first conductivity type, a second epitaxial growth layer formation step of forming a second epitaxial growth layer of the first conductivity type on the first epitaxial growth layer, a trench formation step of forming a trench by performing an anisotropic etching from a trench formation scheduled region on the second epitaxial growth layer through the second epitaxial growth layer and the first epitaxial growth layer to the inside of the semiconductor substrate, a gate oxide film formation step of forming a gate oxide film along a surface of the second epitaxial growth layer and a wall surface of the trench, a polycrystalline silicon layer deposit step of depositing a polycrystalline silicon layer on the gate oxide film, a gate formation step of forming a gate in the trench by performing an arbitrary amount of etching to the polycrystalline silicon layer, its upper portion being coincident with an upper portion of the first epitaxial growth layer, and a drain layer formation step of, forming a drain layer of the first conductivity type on the surface of the second epitaxial growth layer and at the periphery of the trench.
REFERENCES:
patent: 4992390 (1991-02-01), Chang
patent: 5473176 (1995-12-01), Kakumoto
patent: 5578522 (1996-11-01), Nakamura et al.
patent: 6198127 (2001-03-01), Kocon
Harada Hirofumi
Osanai Jun
Adams & Wilks
Chaudhari Chandra
Seiko Instruments Inc.
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