Vertical MOSFET with asymmetric gate structure

Details Vertical MOSFET with asymmetric gate structure Vertical MOSFET with asymmetric gate structure

2002-12-20

2004-02-03

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S286000, C438S304000

Reexamination Certificate

active

06686245

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to the fabrication of a multiple-gate transistor.
2. Description of Related Art
A conventional metal-oxide-semiconductor (MOS) transistor is typically characterized by a structure in which a gate electrode is displaced above the transistor channel region by an intermediate gate dielectric film. The region below the channel may include the bulk substrate or an epitaxial film. The transistor is operated by applying a bias to the gate electrode. The bulk material is likely grounded or biased to a constant voltage. Thus, the conventional transistor may be described as having a single-sided gate since the gate exists on only one side of the channel.
It is generally recognized that single-sided gate transistors inherently exhibit operational characteristics, including leakage current, drive current, and sub-threshold slope, that are less than ideal. These parameters are particularly critical in low power applications such as wireless technology. Multiple-gate transistor structures, in which gate dielectrics and gate electrodes are formed on two (or more) sides of the transistor channel, have been proposed to address this problem.
Typical multiple-gate transistor structures employ a “symmetric” design in which the gate electrode on both sides of the channel is the same material, doping, conductivity, and so forth. Similarly, the gate dielectrics on both sides of the channel are the same. Symmetric multiple gate transistors have been found to suffer from a threshold voltage control problem. For example, n-channel threshold voltages in symmetric multi-gate sub-micron transistors using p+ poly gates and undoped or lightly doped channels have been found to be in the range of 0.9 V whereas threshold voltages of approximately 0.1 to 0.4 V are required for optimum performance. Accordingly, it would be desirable to implement a process enabling the formation of asymmetric, multiple-gate transistors. It would be further desirable if the implemented process did not substantially add to the complexity of the process and did not require the use of new materials and/or equipment.


REFERENCES:
patent: 5413948 (1995-05-01), Pfiester et al.
patent: 5480838 (1996-01-01), Mitsui
patent: 5969384 (1999-10-01), Hong
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6492212 (2002-12-01), Ieong et al.
Wolf et al, “Silicon Processing for the VLSI Era vol. 1—Process Technology”, 1986, Lattice Press, p. 175-182.

Affiliated with

Also associated with

Rating

Vertical MOSFET with asymmetric gate structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vertical MOSFET with asymmetric gate structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical MOSFET with asymmetric gate structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3310664