Vertical MOS transistor

Details Vertical MOS transistor Vertical MOS transistor

2002-11-06

2004-08-17

Lebentritt, Michael (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S240000, C438S244000, C438S149000

Reexamination Certificate

active

06777288

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOS transistor and, more particularly, to a vertical MOS transistor and a method of forming the transistor.
2. Description of the Related Art
A MOS transistor is a well-known element that is one of the fundamental building blocks of many electrical circuits. There are two basic types of MOS transistors, a p-channel or PMOS transistor and an n-channel or NMOS transistor. A PMOS transistor has p+ source and drain regions and a p-channel when conducting, while a NMOS transistor has n+ source and drain regions and an n-channel when conducting.
FIG. 1
shows a cross-sectional view that illustrates one example of a conventional NMOS transistor
100
. As shown in
FIG. 1
, transistor
100
, which is formed in a p-type semiconductor material
110
, such as a substrate or well, has spaced-apart n+ source and drain regions
112
and
114
that are formed in material
110
.
In addition, transistor
100
has a channel region
116
that is located between source and drain regions
112
and
114
. Further, transistor
100
includes a layer of gate oxide
120
that is formed over channel region
116
, and a polysilicon gate
122
that is formed on gate oxide layer
120
over channel region
116
.
In operation, material
110
and source region
112
are often connected to ground when drain region
114
is connected to a positive voltage source, such as 1.2V. As long as the voltage on gate
122
remains below a threshold voltage, substantially no charge carriers flow from source region
112
to drain region
114
(a small leakage current may be present). However, when the voltage on gate
122
equals or exceeds the threshold voltage, transistor
100
turns on and electrons begin to flow from source region
112
to drain region
114
.
FIG. 2
shows a cross-sectional view that illustrates a second example of a conventional NMOS transistor
200
. NMOS transistor
200
is similar to NMOS transistor
100
and, as a result, utilizes the same reference numerals to designate the structures which are common to both transistors.
As shown in
FIG. 2
, transistor
200
differs from transistor
100
in that material
110
is surrounded by an isolation region
210
. In addition, material
110
is not connected to an external bias, such as a substrate or well contact and, as a result, electrically floats. Further, transistor
200
operates the same as transistor
100
.
One of the limitations of transistors
100
and
200
is that the channel lengths of transistors
100
and
200
(the shortest distance between source and drain regions
112
and
114
at the surface of material
110
) are defined by the minimum photolithographic feature size that is provided by the semiconductor fabrication process.
FIGS. 3A-3C
show cross-sectional views that illustrate a MOS structure
300
during a conventional MOS transistor fabrication process. As shown in
FIG. 3A
, MOS structure
300
has a p-type semiconductor material
310
, such as a substrate or well, and a layer of gate oxide
312
that is formed over material
310
.
In addition, MOS structure
300
has a layer of polysilicon
314
that is formed on gate oxide layer
312
, and a mask
316
that is formed on a portion of polysilicon layer
314
. As further shown in
FIG. 3A
, mask
316
has a length L
1
that is equal to the minimum feature size provided by the fabrication process.
Following the formation of MOS structure
300
in
FIG. 3A
, structure
300
is anisotropically etched until the exposed regions of polysilicon layer
314
have been removed from the surface of gate oxide layer
312
. As shown in
FIG. 3B
, the etch forms a gate
318
that has a gate length L
2
that is defined by the length L
1
of mask
316
. Following this, mask
316
is removed.
Next, as shown in
FIG. 3C
, structure
300
is implanted with an n-type dopant to form source and drain regions
320
and
322
. Source and drain regions
320
and
322
can be single heavily-doped n+ implanted regions, or can be lightly-doped n− LDD regions. As further shown in
FIG. 3C
, the implant defines a channel
324
that has a channel length L
3
that is defined by the length L
2
of gate
318
. (Current-generation low temperature annealing and activating processes allow very little lateral diffusion of the dopants.)
As a result, the channel length L
3
is defined by the length L
1
of mask
316
which has the minimum photolithographic feature size that is provided by the fabrication process. Thus, there is a need for a MOS transistor and a method of forming the transistor that allow a channel length to be formed that is smaller than the minimum photolithographic feature size that is provided by the fabrication process.
SUMMARY OF THE INVENTION
The present invention provides a MOS transistor that can be formed to have a channel length that is defined by the thickness of a layer of material that is formed over the substrate. A MOS transistor in accordance with the present invention, which is formed in a semiconductor material of a first conductivity type, includes a first region of a second conductivity type that is formed in the semiconductor material. The MOS transistor also includes a semiconductor region of the first conductivity type that is formed on the semiconductor material over the first region. The semiconductor region has a first side wall, an opposite second side wall, and a top surface.
In addition, the MOS transistor includes a first insulator that is formed on the semiconductor material adjacent to the first side wall, and a second insulator that is formed on the semiconductor material adjacent to the second side wall. Further, the MOS transistor includes a first gate that is formed on the first insulator, and a second region of the second conductivity type that is formed in the top surface of the semiconductor region. The MOS transistor can also include a second gate that contacts the second insulator.
The present invention also includes a method of forming a MOS transistor in a semiconductor material of a first conductivity type. The method includes the steps of forming a first region of a second conductivity type in the semiconductor material, and forming a semiconductor region of the first conductivity type on the semiconductor material. The semiconductor region has a first side wall, an opposite second side wall, and a top surface.
The method also includes the steps of forming a layer of insulation material on the semiconductor material adjacent to the semiconductor region, and forming a layer of conductive material on the layer of insulation material. Further, the method includes the steps of removing the layer of conductive material that lies over the first region, and etching the layer of conductive material to form a first gate and a second gate on the layer of insulation material. The first and second gates are on opposite sides of the semiconductor region.
In the present method, the first region can have a substantially uniform dopant concentration, or a substantially non-uniform dopant concentration. The substantially non-uniform dopant concentration includes a surface region of a light dopant concentration, and a lower region of a heavy dopant concentration that lies below and contacts the surface region.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.


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