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Self-aligned 1 bit local SONOS memory cell and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned 2-bit “double poly CMP” flash...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned active array along the length direction to form...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned bipolar junction transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned bipolar semiconductor device and fabrication...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned bipolar semiconductor device and fabrication...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned body contact for a semiconductor-on-insulator...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned body contact in a semiconductor device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Self-aligned body tie for a partially depleted SOI device...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Self-aligned buried contact pair and method of forming the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned buried strap process using doped HDP oxide

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned cell integration scheme

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned channel transistor and method for making same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned complementary LDMOS

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned conductive spacer process for sidewall control...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned contact for trench DMOS transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned contact process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned contact process comprising a two-layer spacer where

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned contact process for a crown shaped dynamic...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned contact process using a poly-cap mask

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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