Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-26
2001-01-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S655000
Reexamination Certificate
active
06177304
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating salicide and self-aligned contact processes in the fabrication of integrated circuits.
(2) Description of the Invention
In the fabrication of integrated circuit devices, logic products are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode and source and drain regions. The silicided gate and source/drain regions have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
In the production of memory units, the self-aligned contact (SAC) has been widely used to reduce cell size, thus greatly increasing the device density for the CMOS product design. With the advent of Large Scale Integration (LSI) many of the integrated circuits formed on semiconductor substrates comprise several circuit functions on a single chip. For example, memory devices are formed on the same chip as the logic circuits which address them. It is desired to find a method of integrating the salicide and the SAC processes on one wafer so that both high logic performance and high density memory for embedded memory can be achieved.
The standard SAC process needs to use an insulator-capped polysilicon. This makes the process incompatible with the salicide process.
Silicidation has been widely used in the art. Silicidation techniques and self-aligned contacts are discussed in
Silicon Processing for the VLSI Era
, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 144-149 and in
ULSI Technology
, by C. Y. Chang and S. M. Sze, McGraw-Hill, New York, N.Y., c. 1996, pp.397-402 and 487-488. U.S. Pat. No. 5,573,980 to Yoo shows a method of forming a salicided SAC for an SRAM, but with no embedded logic. U.S. Pat. Nos. 5,605,853 and 5,719,079, both to Yoo et al teach formation of a 4T SRAM and floating gate memory and logic device including salicide and a butted contact, but not including a SAC.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits
It is a further object of the invention to provide a process for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory.
Yet another object is to form salicided gate and source/drain regions in the logic circuits of an integrated circuit device while also forming self-aligned contacts in the memory circuits of the same integrated circuit device.
Yet another object of the invention is to form salicided gate and source/drain regions in the logic circuits of an integrated circuit device while also forming simultaneously a self-aligned contact and a butted contact in the memory circuits of the same integrated circuit device.
A still further object of the invention is to form simultaneously a self-aligned contact and a butted contact in the fabrication of an integrated circuit device.
In accordance with the objects of the invention, a method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory is achieved. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas. Gate electrodes and associated source and drain regions are formed on and in the semiconductor substrate wherein the gate electrodes have silicon nitride sidewall spacers. A metal silicide layer is formed on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source and drain regions associated with the gate electrodes using a salicide process. A poly-cap layer is deposited overlying the substrate including the salicided gate electrodes and source and drain regions. The poly-cap layer is selectively removed overlying one of the salicided source and drain regions where a self-aligned contact is to be formed, and overlying another of the salicided source and drain regions and a portion of its associated salicided gate electrode where a butted contact is to be formed. An insulating layer is deposited over the surface of the semiconductor substrate. The insulating layer is etched through to form simultaneously the planned self-aligned contact opening and the planned butted contact opening. The self-aligned contact opening and the butted contact opening are filled with a conducting layer to complete fabrication of the integrated circuit device.
REFERENCES:
patent: 5573980 (1996-11-01), Yoo
patent: 5605853 (1997-02-01), Yoo et al.
patent: 5683922 (1997-11-01), Jeng et al.
patent: 5719079 (1998-02-01), Yoo et al.
patent: 5792684 (1998-08-01), Lee et al.
patent: 5843816 (1998-12-01), Liaw et al.
patent: 5874353 (1999-02-01), Liu et al.
patent: 5885895 (1999-03-01), Liu et al.
patent: 5899742 (1999-05-01), Sun
patent: 6040619 (2000-03-01), Wang et al.
Wolf, “Silicon Processing for the VLSI Era”, vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, (1990), pp. 144-149.
Chang et al., “ULSI Technology”, The McGraw-Hill Companies, Inc., NY, (1996), pp. 397-402 and 486-487.
Lai Mau Lam
Li Weining
Lin Yung-Tao
Wee Tin Tin
Chartered Semiconductor Manufacturing Ltd.
Niebling John F.
Pike Rosemary L. S.
Pompey Ron
Saile George O.
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