Self-aligned contact process comprising a two-layer spacer where

Details Self-aligned contact process comprising a two-layer spacer where Self-aligned contact process comprising a two-layer spacer where

1999-02-01

2000-05-02

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, 438586, 438595, 438948, H01L 21336, H01L 213205

Patent

active

060571969

ABSTRACT:
A self-aligned contact process for fabricating semiconductor devices on a semiconductor substrate is described. The present process comprises providing two gates structure on a semiconductor substrate, wherein the gate structure comprises a gate and a passivation layer on the top surface thereof. A buffer layer is conformally overlaid on the gate structure, passivation layer and the semiconductor substrate. A photoresist material is formed on the semiconductor substrate to a level between the top surface of the passivation layer and interface between the passivation layer and gate. The buffer layer is removed to the level of the photoresist layer. Next, the photoresist material is removed. A spacer is formed on the sidewall of the buffer layer and the passivation layer of the gate structure. An insulating layer is formed on the semiconductor substrate and then, a contact opening is formed therein to expose the semiconductor substrate.

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patent: 5466637 (1995-11-01), Kim
patent: 5714413 (1998-02-01), Brigham et al.
patent: 5736442 (1998-04-01), Mori
patent: 5807779 (1998-09-01), Liaw

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