Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-25
2001-08-14
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S639000
Reexamination Certificate
active
06274426
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create a self-aligned contact opening, for a capacitor structure.
(2) Description of Prior Art
The advent of the self-aligned contact, (SAC), opening, has contributed to the objective of increasing the density of semiconductor chips. The SAC opening, as used with metal oxide semiconductor field effect transistors, (MOSFET), allows the entire width of a source/drain region, located between gate structures, to be exposed, and to be subsequently contacted by an overlying conductive structure. The SAC opening comprises the exposure of the entire source/drain region, located in the space between gate structures, as well as the exposure of a portion of insulator capped, gate structures. Thus the SAC opening eliminates the need to form a fully landed contact hole to the source/drain region, and thus allows the space between the gate structures, to be less than the minimum photolithographic feature used, resulting in increased device density. The use of a SAC opening is made possible via use a reactive ion etching, (RIE), procedure, featuring a high etch rate ratio, or selectivity, between a silicon oxide layer, located between, as well as overlying, the insulator capped, gate structures, and the silicon nitride, or silicon oxynitride layer, used for the hard mask, or capping layer. However difficulties can be encountered earlier, when depositing the silicon oxide layer, in the high aspect ratio space between the insulator capped, gate structures. Undesirable seams or voids, can form at the point where the silicon oxide layers, on the sides of the insulator capped, gate structures, converge. The subsequent SAC opening will expose the seam or void, at the perimeter of the SAC opening, presenting a possible leakage or shorting mechanism, between the conductive structure formed in the SAC opening, and adjacent conductive structures.
This invention will provide a process in which the seam or void, in the silicon oxide layer, is repaired by forming a silicon nitride liner on the exposed sides of the silicon oxide layer, at the perimeter of the SAC opening. In addition this invention will provide a process used to recess back a top portion of the silicon nitride liner, however still leaving a bottom portion of the silicon nitride liner to protect the voids or seams in the portion of the silicon oxide layer located between the gate structures. This in turn allows a top portion of the silicon oxide layer to be recessed via a selective wet etch procedure, after the formation of a polysilicon storage node structure on the inside walls of the SAC opening, resulting in the additional exposure of polysilicon storage node surface, and thus increased capacitance for a crown shaped capacitor structure, located in the SAC opening. Prior art, such as Yang et al, in U.S. Pat. No. 5,792,689, as well as Chen, in U.S. Pat. No. 5,736,441, describe crown shaped capacitors, in SAC openings, however neither prior art describe the process for forming a silicon nitride liner, on the sides of the SAC opening, located between gate structures.
SUMMARY OF THE INVENTION
It is an object of this invention to create a crown shaped, capacitor structure, in a SAC opening.
It is another object of this invention to form a silicon nitride liner, on the inside walls of the SAC opening, formed in a silicon oxide layer, to repair voids or seams in the silicon oxide layer, now exposed at the perimeter of the SAC opening.
It is still another object of this invention to remove the top portion of the silicon nitride liner from the walls of a top portion of the SAC opening, to allow a polysilicon storage node structure to interface a silicon oxide layer, in top portion of the SAC opening, while allowing the polysilicon storage node structure to reside on the silicon nitride liner, in the bottom portion of the SAC opening.
It is still yet another object of this invention to recess a top portion of the silicon oxide layer, to expose a portion of the outside surfaces of the polysilicon storage node structure, creating a crown shaped, polysilicon storage node structure.
In accordance with the present invention a process for fabricating a crown shaped, capacitor structure, in a SAC opening, formed in a silicon oxide layer, and featuring a silicon nitride liner, used on the walls of the silicon oxide layer, exposed in the bottom portion of the SAC opening, is described. After creation of a source/drain region, in a semiconductor substrate, formed in the space between insulator capped, gate structures, and comprised with silicon nitride spacers, a thick silicon oxide layer is deposited. A SAC opening is formed in the thick silicon oxide layer, exposing the source/drain region, located between insulator capped, gate structures, and exposing a portion of the top surface of the insulator capped, gate structures. A thin silicon nitride liner is formed on the sides of the SAC opening. An organic plug is formed in the bottom portion of the SAC opening, allowing an isotropic etching procedure to remove the exposed portion of silicon nitride liner, from the sides of the top portion of the SAC opening. After formation of a polysilicon storage node structure, on the exposed inside surfaces of the SAC opening, the thick silicon oxide layer is recessed, resulting in a crown shaped, polysilicon storage node structure comprised of: upper polysilicon features, extending upwards from the bottom portion of the thick silicon oxide layer; lower polysilicon features, located on the sides of the bottom portion of the thick silicon oxide layer, in the SAC opening; and comprised of a horizontal polysilicon feature, located at the bottom of the SAC opening, overlying the source/drain region, and connecting the vertical polysilicon features, located on the sides of the SAC opening. After formation of a capacitor dielectric layer, on the exposed surfaces of the polysilicon storage node structure, a polysilicon upper, or cell plate is formed, resulting in a crown shaped capacitor structure, in a SAC opening, with the bottom portion of the polysilicon storage node structure, of the crown shaped capacitor structure, interfacing a silicon nitride liner, which in turn was formed on the sides of the bottom portion of the SAC opening.
REFERENCES:
patent: 5482894 (1996-01-01), Havemann
patent: 5643833 (1997-07-01), Tsukamoto
patent: 5721154 (1998-02-01), Jeng
patent: 5723374 (1998-03-01), Huang et al.
patent: 5736441 (1998-04-01), Chen
patent: 5763306 (1998-06-01), Tsai
patent: 5780338 (1998-07-01), Jeng et al.
patent: 5792689 (1998-08-01), Yang et al.
Chiang Min-Hsiung
Lee Yu-Hua
Wu James (Cheng-Ming)
Ackerman Stephen B.
Meier Stephen D.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Thomas Toniae M.
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