Self-aligned contact for trench DMOS transistors

Details Self-aligned contact for trench DMOS transistors Self-aligned contact for trench DMOS transistors

1999-11-23

2001-02-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S361000, C438S364000

Reexamination Certificate

active

06184092

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to MOS (metal oxide semiconductor) transistor devices. Specifically, the present invention relates to trench DMOS (double diffused MOS) transistors in which a self-aligned contact structure allows the contact to be fabricated without defining on a mask.
BACKGROUND OF THE INVENTION
Trench DMOS transistors are widely used in integrated circuits for power transistors. The gate electrode is a conductive material, which located in a trench in the transistor substrate, where the sidewalls and bottom of the trench are insulated with silicon dioxide.
In a typical discrete trench DMOS circuit, several trench DMOS transistors are fabricated in parallel. Therefore, on a typical discrete trench DMOS semiconductor, the trench DMOS devices share a common drain contact (the substrate), their sources are all shorted together with metal, and their gates are shorted together with polysilicon. It is often physically constructed using an array or matrix of smaller transistors all connected in parallel. For a discrete trench DMOS semiconductor, it is desirable to maximize the conductivity per unit area of trench DMOS transistor array when it is turned “on” by the gate.
In order to increase the density of the trench DMOS devices on a chip, it is desirable to minimize the contact size so that adjacent neighboring transistors (trenches) can be fabricated as closely as possible to each trench DMOS transistor pair. However, each masking step requires a mask alignment and therefore results in a possible alignment error, undesirably reducing yield. Expected mask alignment errors can be factored into the device dimensions in order to minimize the adverse affect on yield, but this approach increases the cell dimensions, thereby reducing the density of the trench DMOS transistors on the semiconductor and correspondingly decreasing the conductivity per unit area.
FIGS. 4A-4C
schematically show the process flow in forming non-self-aligned contacts of trench DMOS in the prior art.
FIG. 4A
shows a pair of closely packed trenches
20
and
21
in semiconductor substrate
10
. The trench
20
and trench
21
are substantially the same. Inside the trenches
20
and
21
, an underlying dielectric layer
31
and a polycrystalline silicon plug
15
are deposited. An (ILD) layer
42
is then deposited over the surface of the semiconductor substrate
10
and trenches
20
,
21
. The ILD layer
42
can be formed by a low temperature oxidation process with material of silicon oxide, tetraethylanthosilicate phospsilicate glass boronophosilicate glass or any combination of above. Then a photolithographic photoresist layer
17
is applied to form contact patterns. After that, as shown in
FIG. 4C
, ILD layer
42
is etched to expose contact regions
18
a
to
18
c
, and a plurality of ILD islands (noted as
32
a
-
32
d
) stay on semiconductor surface and trenches
20
,
21
.
After stripping off the photoresist layer
17
, a conductive metal layer
19
is deposited to cover the ILD islands
32
a
-
32
d
and those exposed contact regions
18
a
-
18
c
. However, as mentioned above, the spacing
101
between trench
20
and trench
21
should be designed larger than the necessary contact size in order to compensate for the possible alignment error. Thereby, it is impossible to get the most closely packed devices (trenches
20
and
21
) in the prior art process described above.
Since it is generally desirable to reduce the costs of manufacturing trench DMOS devices, it would be desirable to design devices as closely packed as possible. Therefore, under the same condition of the photolithographic resolution and alignment capability, it is desirable to eliminate the ILD islands (
32
a
and
32
b
) on top of trench
20
and trench
21
, respectively, in order to design the smallest spacing
101
between the trench edges of trench
20
and
21
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of fabricating trench DMOS transistors structures with the contact to the transistor's source and body self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Therefore, the distance between the trench edges, which is the source and body region, can be reduced. As a result, the packing density of the transistors is increased dramatically. This also gives rise to much improved device performance in terms of lower on-resistance and higher current driving capability.
The method for forming a self-aligned contact for trench DMOS transistors, as shown in
FIGS. 3A-3D
, which includes: providing a semiconductor substrate
10
; etching trenches
20
and
21
into the semiconductor substrate
10
at selected locations on the surface of the semiconductor substrate
10
, trenches
20
and
21
are substantially the same; forming a first dielectric layer
31
over the sides and bottom of the trenches
20
and
21
; forming plugs
32
a
and
32
b
inside the trenches
20
and
21
, respectively, over the first dielectric layer
31
, and the top of the plugs
32
a
and
32
b
being below the top of the trenches
20
and
21
; forming a second dielectric layer
16
over the top of the plugs (
32
a
,
32
b
); forming an silicon nitride layer
41
over the second dielectric layer
16
and the semiconductor surface; forming an ILD layer
42
over the silicon nitride layer
41
; defining contact patterns to expose pre-selected regions by using photolithographic process; dry etching the ILD/silicon nitride bi-layers to expose pre-selected contact regions
18
b
-
18
c
and ILD islands
32
c
-
32
d
; forming a conductive layer
19
over the second dielectric layer
16
, ILD islands
32
c
-
32
d
and the exposed semiconductor surface for ohmic contact regions
18
a
-
13
c.


REFERENCES:
patent: 4728606 (1988-03-01), Bukhman et al.
patent: 4835115 (1989-05-01), Eklund
patent: 5830797 (1998-11-01), Cleeves
patent: 5939335 (1999-08-01), Arndt et al.
patent: 6020621 (2000-02-01), Wu

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