Self-aligned contact process

Details Self-aligned contact process Self-aligned contact process

1999-04-20

2001-10-23

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S239000, C438S229000

Reexamination Certificate

active

06306701

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to process for fabricating semiconductor devices, and more particularly to a self-aligned contact process for fabricating semiconductor devices.
2. Description of the Related Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to reduce the size thereof for faster but lower cost devices. To enhance the integration on the semiconductor, for example, in the structure of a Dynamic Random Access Memory (DRAM), reductions are proposed in the source/drain contact areas on metal oxide semiconductor (MOS). Therefore, while the areas for source/drain are reduced, the formation of contact openings on the source/drain in MOS to be filled with conductive material and the alignment thereof are important tasks.
A self-aligned contact process is developed for achieving the above goals, which process allows smaller devices to be constructed.
FIGS. 1A
to
1
C schematically illustrate the cross-sectional representations of a conventional self-aligned contact process.
With reference to
FIG. 1A
, a gate oxide
105
and a gate
110
are provided on a semiconductor substrate
100
. The gate
110
is composed of a doped polysilicon layer
120
and a tungsten silicide layer
130
. A silicon nitride layer
140
is used as a passivation layer for the gate
110
.
In
FIG. 1B
, a conformal liner layer
150
is formed on the gate oxide
105
, the gate
110
and the silicon nitride layer
140
. A spacer
160
is formed on the sidewall
155
of the liner layer
150
. The material of the liner layer
150
is silicon oxide, while the material of the spacer is silicon nitride.
Referring to
FIG. 1C
, an insulating layer
170
is formed by chemical vapor deposition (CVD) and then is etched by photolithography. The material of an insulating layer
170
is silicon oxide. In this process, since the top surface and the side wall of the gate
110
are protected by the silicon nitride layer
140
and the spacer
160
, a selective etching of silicon oxide
170
is performed to expose the substrate between the spacers
160
as a contact opening
180
. However, since both the material of the liner layer
150
and the insulating layer
170
are silicon oxide, when selectively etching the insulating layer
170
, the liner layer
150
is simultaneously etched to result in a defect
190
. Furthermore, in the subsequent procedure, before the conductive material fills the contact opening
180
, the semiconductor substrate is stripped with RCA solution (H
2
O
2
/NH
4
OH/H
2
O solution) which can etch away the silicon oxide. During the step of stripping the substrate with RCA solution, the defect
190
is etched more to expose the tungsten silicide
130
, and even to expose the doped polysilicon layer
120
. When filling the contact opening
180
with conductive material for forming the conductive line, the defect
190
is filled at same time. A short occurs between the gate
110
and conductive line.
One approach for resolving the above-mentioned problem is to employ a thinner liner layer
150
to reduce the possibility of etching the liner layer
150
. Typically, the thickness of the liner layer
150
should be at least 200 Å. In this approach, a thickness of 100-200 Å for the liner layer
150
is suggested. However, one purpose of the liner layer
150
is to decrease stress in the spacer
160
during the thermal treatment in the following procedures. Therefore, the thinner liner layer will result in the dislocation of the substrate.
Another approach for resolving the above-mentioned problems is the formation of a liner layer by a thermal oxidation process, rather than by chemical vapor deposition as used in the conventional process. In the thermal oxidation process, the sidewall of the doped polysilicon layer and tungsten silicide layer of the gate is formed on a passivation layer, while no oxide is formed on the top surface of the gate, which is silicon nitride. In such a case, the liner layer on the sidewall of the gate is embedded in the spacer. Therefore, no defect in the liner layer is formed during the etching process. However, an additional oxidation process is incorporated and thermal treatment results in adversely affecting the substrate, such as causing a dislocation of the substrate.
Therefore, a need exists to avoid the occurrence of a short between a conductive line and a gate in the self-aligned contact process.
SUMMARY OF THE INVENTION
The invention provides a self-aligned contact process to insulate a gate and a conductive material filling in a contact. An occurrence of short between the conductive material and the gate can thus be avoided.
The invention provides a self-aligned contact process. A substrate is provided. A gate including a polysilicon layer and a metal silicide layer is formed on the substrate. A cap layer is formed on the gate to protect the gate. A first spacer is formed on the sidewall of the gate. A first ion implantation is performed using the gate and the first spacer as a first mask to form lightly doped regions in the substrate. A conformal liner layer is formed on the cap layer the first spacer and the substrate. An insulating layer is formed on the conformal liner layer. A part of the insulating layer and a part of the liner layer are removed until exposing the cap layer. A part of the liner layer remaining on the first spacer and a part of the insulating layer remaining on the remaining liner layer are used as a second spacer. A second ion implantation is performed to form source/drain regions with lightly doped drain (LDD) structures in the substrate beside the second spacer. An inter-layer dielectric layer is formed over the substrate and then is etched to form a contact opening therein to expose a part of the source/drain regions.
Since the spacers and the liner layer are made from different materials, the etching selectivity between the spacers and the liner layer is large. The first spacer can prevent the gate from being damaged while forming the contact opening by self-alignment. The first spacer serves as an offset spacer. The lightly doped regions are formed after forming the first spacer so that a distance between the lightly doped regions becomes longer than a distance between conventional lightly doped regions. The short channel effect can thus be prevented. The gate, the gate oxide layer and the lightly doped regions constitute a structure that serves as a parasitic capacitor. A capacitance of the parasitic capacitor decreases according to the increased distance between the lightly doped regions.
Furthermore, the first spacer is located on the sidewall of the gate so that the metal silicide layer is not attacked while etching the inter-layer dielectric layer to form the contact opening. This can suppress gate resistance degradation and the process window for self-aligned contact formation can be enhanced.


REFERENCES:
patent: 5436482 (1995-07-01), Ogoh
patent: 5747373 (1998-05-01), Yu
patent: 5849616 (1998-12-01), Ogoh
patent: 5895239 (1999-04-01), Jeng et al.

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