Self-aligned 2-bit “double poly CMP” flash...

Details Self-aligned 2-bit “double poly CMP” flash... Self-aligned 2-bit “double poly CMP” flash...

2007-05-08

2007-05-08

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S316000, C257S319000, C438S201000

Reexamination Certificate

active

10532292

ABSTRACT:
Fabrication of a memory cell, the cell including a first floating gate stack (A), a second floating gate stack (B) and an intermediate access gate (AG), the floating gate stacks (A, B) including a first gate oxide (4), a floating gate (FG), a control gate (CG; CGl, CGu), an interpoly dielectric layer (8), a capping layer (6) and side-wall spacers (10), the cell further including source and drain contacts (22), wherein the fabrication includes: defining the floating gate stacks in the same processing steps to have equal heights; depositing over the floating gate stacks a poly-Si layer (12) with a larger thickness than the floating gate stacks' height; planarizing the poly-Si layer (12); defining the intermediate access gate (AG) in the planarized poly-Si layer (14) by means of an access gate masking step over the poly-Si layer between the floating gate stacks and a poly-Si etching step.

REFERENCES:
patent: 5278439 (1994-01-01), Ma et al.
patent: 5364806 (1994-11-01), Ma et al.
patent: 5414693 (1995-05-01), Ma et al.
patent: 6329248 (2001-12-01), Yang
patent: 6462375 (2002-10-01), Wu
patent: WO 01 67517 (2001-09-01), None

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