Salicide field effect transistors with improved borderless...

Details Salicide field effect transistors with improved borderless... Salicide field effect transistors with improved borderless...

2000-02-07

2002-01-01

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000, C438S305000, C438S592000

Reexamination Certificate

active

06335249

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making an improved borderless contacts integrated with salicide field effect transistors. The method utilizes a contact implant and a delayed second rapid thermal anneal (RTA-2) to make a new contact structure having lower source/drain-to-substrate leakage currents and thereby higher product yields than the prior art borderless contact structures.
(2) Description of the Prior Art
As the semiconductor industry moves to smaller device feature sizes for ultra large scale integration (ULSI), the circuit performance is expected to improve. To achieve these smaller feature sizes it is necessary to use self-aligned techniques, such as self-aligned silicide (SALICIDE) processes for making field effect transistors (FETs). To further increase circuit density it is also necessary to etch contact openings that extend over the edges of underlying contact areas, commonly referred to as borderless contacts. One structure on semiconductor integrated circuits where borderless contacts are of particular importance for increasing circuit density is the contacts to the shallow diffused source/drain areas of the salicide FET.
Unfortunately when making salicide FETs with borderless contacts to source/drain areas several processing problems arise that result in electrical shorts and there-fore degrade the product yield. To better understand the problem associated with making these borderless contacts a schematic cross section view of a conventional Salicide FET device in and on a device area is shown for the prior art in FIG.
1
. These conventional Salicide FETs are formed on a semiconductor substrate
10
, composed of a single crystal silicon (Si). Field oxide
12
regions are formed first in and on the substrate
10
surface to electrically isolate device areas. The preferred isolation for current high density circuits is a shallow trench isolation (STI)
12
. The detailed process steps are not shown for making the STI, but consist of forming a pad oxide and depositing a silicon nitride hard mask layer. The silicon nitride (Si
3
N
4
) layer is patterned to leave portions over the device areas and shallow trenches
2
are etched in the substrate between the device areas. The trenches are then filled by chemical vapor deposited with an insulating material, such as silicon oxide (SiO
2
). The CVD-SiO
2
is etched or chemical-mechanically polished back to the hard mask to form the STI
12
. The hard mask and pad oxide, which is not shown in
FIG. 1
, are then selectively removed, for example using a hot phosphoric acid etch to remove the Si
3
N
4
followed by a buffered hydrofluoric acid (BHF) to remove the pad oxide A gate oxide
14
is formed on the device areas and conductively doped polysilicon layer is deposited and patterned by anisotropic plasma etching to form the FET gate electrode
16
. Next, a first ion implantation is carried out to form lightly doped source/drain region
17
in the device areas adjacent to the FET gate electrode. A conformal insulating, such as a chemical vapor deposited (CVD) silicon oxide (SiO
2
) layer, is deposited and anisotropically plasma etched back to form sidewall spacers
18
. A second ion implantation is then carried out to form low resistant diffused source/drain contact areas
19
in and on the silicon substrate. After removing any native oxide that may have grown on the polysilicon gate electrode
16
and the silicon source/drain contact areas
19
a refractory metal, such as Titanium (Ti) is deposited. The substrate
10
is then subjected to a first rapid thermal anneal to form a Titanium silicide (TiSi
x
)
22
on the exposed polysilicon gate electrode
16
and on the source/drain contact areas
19
. The unreacted Ti on the oxide surfaces (e.g. spacers
18
, STI
12
) using a wet etching solution. A second RTA is then carried out to complete the TiSi
2
phase transition. The second RTA converts the TiSi
x
to a stable TiSi
2
layer having low sheet resistance. When cobalt (Co) is used the second RTA converts the CoSi
x
to a stable CoSi
2
silicide layer also having a low sheet resistance. The two-step process is commonly used rather than a single-step to avoid rapid diffusion of the Si atoms in the metal (Ti or Co) layer that would result in bridging across the sidewall spacers and between the source/drain areas and polysilicon gate electrodes. Next, a relatively thin conformal etch-stop/barrier layer
24
is deposited, such as a silicon nitride (Si
3
N
4
) or a silicon oxynitride (SiON) layer. A relatively thick interlevel dielectric (ILD) layer
28
, for example, a CVD-SiO
2
and/or a doped glass, such as a borophosphosilicate glass (BPSG), is deposited to electrically insulated the FETs on the silicon substrate
10
from the next level of integration. Now, as commonly practiced in the industry, a photoresist mask and an aniso-tropic plasma etch are used to etch borderless contact openings
2
in the ILD layer
28
to the diffused source/drain contact areas
19
. Because of the nonuniformity in the ILD layer
28
across the substrate and the nonuniformities in the etch rate for etching the contact openings
2
across the substrate, it is necessary to overetch the contact openings
2
to insure that the multitude of contacts openings formed are all completely opened. Unfortunately, when these borderless contact openings
2
are etched that extend over the STI
12
, the STI is over etched in the region X at the STI-silicon substrate interface. When the over etched region X extends below the shallow diffused junction x
j
for either N or P doped source/drain contacts
19
and the silicon substrate
10
are electrically shorted and the circuits fail.
Numerous methods for making improved Salicide FETs, and borderless contacts have been reported in the literature. In U.S. Pat. No. 5,858,846 to Tsai et al. a method for making salicide FETs is describe in which arsenic ions are implanted in a titanium (Ti) metal layer prior to annealing to inhibit Si diffusion in Ti and eliminate bridging between the source/drain and gate electrode. In U.S. Pat. No. 5,744,395 to Shue et al., a Ti layer is deposited at an elevated temperature to form a silicide which is removed in a wet etch and then requires only a single RTA. In U.S. Pat. No. 5,702,972 to Tsai et al., a double spacer method is described in which the second spacer is removed after the silicide is formed. In U.S. Pat. No. 5,899,742 to Sun, a method is described for making aligned local inter-connections and contacts simultaneously to FETs. The method is compatible with salicide FETs, but he does not address the overetch problem. In U.S. Pat. No. 5,840,624 to Jang et al. a method is described for etching borderless contacts on multilevel metal layers without overetching, but does not address etching contacts to shallow diffused junction adjacent to STI. Therefore there is still a need in the industry to provide salicide FET structures with better borderless contacts to the source/drain contacts when shallow trench isolation (STI) is used for advance circuit structures.
SUMMARY OF THE INVENTION
A principal object of this invention is to provide a process and structure for making salicide field effect transistors (FETs) with improved borderless contacts to the source/drain contact areas for increased product (device) yield.
It is another object of this invention to achieve these improved borderless contacts by ion implanting a contact dopant in the contact openings after a first rapid thermal anneal (RTA) and prior to a second RTA used to form the salicide FETS. This implant results in a modified source/drain contact diffused junction profile in the silicon substrate under and adjacent to any unintentionally overetched field oxide (STI) regions at the STI-substrate interface, thereby reducing source/drain-to-substrate electrical shorts.
It is still another object of the invention to provide an improved bord

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