Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-17
2002-05-14
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06387757
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for fabricating split gate field effect transistor (FET) devices, as employed within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for fabricating split gate field effect transistor (FET) devices with enhanced properties, as employed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
In addition to conventional semiconductor integrated circuit microelectronic fabrications having formed therein conventional field effect transistor (FET) devices and conventional bipolar junction transistor (BJT) devices whose transient operation provides for data storage and transduction capabilities within the conventional semiconductor integrated circuit microelectronic fabrications, there also exists within the art of semiconductor integrated circuit microelectronic fabrication non-volatile semiconductor integrated circuit microelectronic fabrications, and in particular non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrically erasable programable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, whose data storage and transduction capabilities are not predicated upon transient operation.
Although non-volatile semiconductor integrated circuit microelectronic memory fabrications, such as but not limited to electrical erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrications, may be fabricated while employing any of several semiconductor integrated circuit microelectronic devices, a particularly common semiconductor integrated circuit microelectronic device employed within an electrically erasable programmable read only memory (EEPROM) non-volatile semiconductor integrated circuit microelectronic memory fabrication is a split gate field effect transistor (FET) device.
A split gate field effect transistor (FET) device is in part analogous in structure and operation with a conventional field effect transistor (FET) device insofar as a split gate field effect transistor (FET) device also comprises formed within a semiconductor substrate a channel region defined by a pair of source/drain regions also formed within the semiconductor substrate, wherein at least the channel region of the semiconductor substrate has formed thereupon a gate dielectric layer which separates a gate electrode from the channel region of the semiconductor substrate, but a split gate field effect transistor (FET) device is nonetheless distinguished from a conventional field effect transistor (FET) device by employing rather than a single gate electrode positioned upon the gate dielectric layer and completely covering the channel region of the semiconductor substrate: (1) a floating gate electrode positioned upon the gate dielectric layer and covering over only a portion of the channel region defined by the pair of source/drain regions (such portion of the channel region also referred to as a floating gate electrode channel region); and (2) a control gate electrode positioned over the gate dielectric layer and covering a remainder portion of the channel region while at least partially covering and overlapping the floating gate electrode while being separated from the floating gate electrode by an inter-gate electrode dielectric layer (such remainder portion of the channel region also referred to as a control gate electrode channel region).
In order to effect operation of a split gate field effect transistor (FET) device, particular sets of voltages are applied to the control gate electrode, the source/drain regions and the semiconductor substrate in order to induce or reduce charge within the floating gate electrode (which is otherwise fully electrically isolated) and thus provide conditions under which the floating gate electrode within the split gate field effect transistor (FET) device may be programmed, erased and/or read.
While split gate field effect transistor (FET) devices are thus desirable within the art of semiconductor integrated circuit microelectronic fabrication for providing semiconductor integrated circuit microelectronic fabrications with non-volatile data storage characteristics, split gate field effect transistor (FET) devices are nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within non-volatile semiconductor integrated circuit microelectronic fabrications split gate field effect transistor (FET) devices with enhanced properties, and in particular with enhanced alignment properties.
It is thus towards the goal of providing for use within semiconductor integrated circuit microelectronic fabrications, and in particular within semiconductor integrated circuit microelectronic memory fabrications, methods for fabricating split gate field effect transistor (FET) devices with enhanced properties, and in particular with enhanced alignment properties, that the present invention is directed.
Various non-volatile semiconductor integrated circuit microelectronic devices with enhanced alignment properties, and methods for fabrication thereof, have been disclosed within the art of non-volatile semiconductor integrated circuit microelectronic fabrication.
For example, Chien et al., in U.S. Pat. Nos. 6,001,690 and 6,069,042, disclose a pair of methods for forming, with enhanced dimensional properties, self aligned spacer layers which in turn may be employed as ion implant mask layers for forming, with enhanced alignment properties, split gate field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications. To realize the foregoing objects, a first of the pair of methods employs a partial isotropic/anisotropic etching of a blanket silicon nitride layer when forming a self aligned silicon nitride spacer layer adjacent a floating gate electrode within a split gate field effect transistor (FET) device, rather than a solely anisotropic etching of the blanket silicon nitride layer when forming the self aligned silicon nitride spacer layer adjacent the floating gate electrode within the split gate field effect transistor (FET) device. In addition, and also to realize the foregoing objects, a second of the pair of methods employs a blanket multi-layer laminated silicon oxide/silicon nitride layer, rather than a blanket silicon nitride layer only, when forming while employing an anisotropic etching method a multi-layer laminated silicon oxide/silicon nitride spacer layer adjacent a floating gate electrode within a split gate field effect transistor (FET) device.
In addition, Chen, in U.S. Pat. No. 6,071,777, discloses a method for forming, with enhanced alignment of a drain region with respect to a floating gate electrode and thus with a resulting enhanced control gate electrode channel definition, a split gate field effect transistor (FET) device within a semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the method employs a laminate of a doubly apertured patterned silicon nitride mask layer having formed asymmetrically thereupon a singly apertured patterned photoresist mask layer, wherein the laminate is successively delaminated in defining the drain region with respect to the floating gate electrode within the split gate field effect transistor (FET) device within the semiconductor integrated circuit microelectronic fabrication.
Finally, Chen, in U.S. Pat. No. 6,091,104, discloses a stacked gate field effect transistor (FET) device which may be fabricated with enhanced alignment for use within a semiconductor integrated circuit microelectronic fabrication. To realize the foregoing object, the stacked gate field effect transistor (FET) device employs a control gate electrode as a self aligning structure
Chang Chuan-Li
Chu Wen-Ting
Hsieh Chia-Da
Kuo Di-Son
Tsaur Sheng-Wei
Booth Richard
Taiwan Semiconductor Manufacturing Company Ltd
Tung & Associates
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