SAC method for embedded DRAM devices

Details SAC method for embedded DRAM devices SAC method for embedded DRAM devices

2001-03-16

2002-11-26

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S672000

Reexamination Certificate

active

06486033

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of removing the gate silicon nitride in the logic area of an embedded DRAM for improved self-aligned contact (SAC) processing in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, embedded dynamic random access (DRAM) devices have both memory cells and logic cells formed on a single silicon chip. Embedded DRAM is capable of transferring large quantities of data at very high speeds. A gate silicon nitride capping layer is required for the DRAM source/drain regions and self-aligned contact formation. However, the silicon nitride capping layer limits DRAM capacitor size and SAC size. Furthermore, metal contact etching through the thick silicon nitride layer on top of the gate is a challenge due to serious substrate loss in the source/drain regions.
For example,
FIG. 1
illustrates the logic portion of a partially completed integrated circuit device. Gate electrodes comprise a polysilicon layer
16
, an overlying silicide layer
18
, a capping oxide layer
20
, and a capping silicon nitride layer
22
. Silicon nitride sidewall spacers
24
and silicon nitride liner layer
28
have also been formed on the gate electrodes, as shown. The DRAM portion of the integrated circuit device, not shown, needs the silicon nitride layers in order to form self-aligned contacts. However, in the logic portion shown in
FIG. 1
, in order for the metal contact
34
to contact the silicide layer
18
, the contact opening must be etched through the thick silicon nitride layer
28
/
22
. This results in overetching of the contact
38
into the silicon substrate, as shown by
40
.
FIG. 2
shows an example of another problem in the prior art. A DRAM portion of a partially completed integrated circuit device is shown in FIG.
2
. As in the logic portion shown in
FIG. 1
, gate electrodes comprise a polysilicon layer
16
, an overlying silicide layer
18
, a capping oxide layer
20
, and a capping silicon nitride layer
22
. Silicon nitride liner layer
28
has also been formed over the gate electrodes. Self-aligned contact openings are made through the dielectric layer
30
to node contacts
32
. These openings are filled, for example, with polysilicon plugs
42
. If there is misalignment during patterning of the metal contact opening, the opening will be etched through the silicon nitride capping layer
22
and the oxide layer
20
, causing a short
60
to the gate. A possible solution to this problem is to enlarge the polysilicon plug
42
, as shown by dotted lines
63
. However, this solution will limit capacitor size, as shown by
65
.
It is desired to provide a process for forming metal contacts in both the logic and DRAM regions simultaneously while avoiding serious substrate loss in the logic area and preventing metal contact shorting to the gate without increasing SAC size.
U.S. Pat. No. 6,074,908 to Huang, U.S. Pat. No. 5,998,251 to Wu et al, U.S. Pat. No. 6,117,725 to Huang, and U.S. Pat. No. 6,069,037 to Liao disclose various embedded DRAM processes. U.S. Pat. No. 5,633,188 to Ogawa, U.S. Pat. No. 5,798,289 to Ajika et al, and U.S. Pat. No. 6,127,260 to Huang disclose various DRAM and other memory processes.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide an effective and very manufacturable method for forming embedded DRAM devices in the fabrication of integrated circuits.
It is a further object of the invention to provide a process for forming metal contacts simultaneously in both logic and memory areas in the fabrication of integrated circuits.
Another object is to remove the capping silicon nitride layer in the logic area to increase the metal contact etching process window in the fabrication of logic devices with embedded memory.
Yet another object is to provide a process for forming metal contacts in both the logic and DRAM regions simultaneously while avoiding serious substrate loss in the logic area and preventing metal contact shorting to the gate without increasing SAC size.
In accordance with the objects of the invention, a method for forming logic circuits with embedded memory is achieved. Isolation regions are formed in and on a semiconductor substrate separating active areas wherein active areas comprise at least one logic area and at least one memory area. Gate electrode stacks are formed in the active areas comprising a polysilicon layer, a silicide layer, a first oxide layer, and a first nitride layer. The semiconductor substrate and gate electrode stacks are covered with a first mask layer. The first mask layer is partially removed in the logic areas to expose the first nitride layer. The exposed first nitride layer is removed to expose the first oxide layer in the logic areas. The first mask layer is removed in both logic and memory areas. Lightly doped regions are formed. Nitride spacers are formed on the gate electrode stacks in the logic areas. Source/drain regions are formed in the logic areas. A second nitride layer is deposited overlying the logic areas and memory areas. A second oxide layer is formed overlying the second nitride layer. Memory devices are formed in the memory areas. Contact openings are etched simultaneously through the second oxide layer in both the logic and memory areas. The contact openings are filled with a metal layer to complete fabrication of the integrated circuit device.
More particularly, in accordance with the objects of the invention, a method for forming logic circuits with embedded memory is achieved. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas which include at least one logic device area and at least one memory device area. Gate electrode stacks are formed in the device areas wherein the gate electrode stacks comprise a first polysilicon layer, an overlying silicide layer, an overlying first oxide layer, and a topmost capping silicon nitride layer. The semiconductor substrate and the gate electrode stacks are covered with a photoresist layer. The memory areas are covered with a mask. The photoresist layer in the logic areas not covered by the mask is exposed to low energy. The exposed photoresist layer in the logic areas is partially developed away to a height approximately equal to the height of the topmost capping silicon nitride layer. The topmost capping silicon nitride layer is etched away in the logic areas. The photoresist layer is removed in both the logic areas and the memory areas. Lightly doped regions are implanted in both the logic areas and the memory areas. A first silicon nitride layer is deposited over the semiconductor substrate and the gate electrode stacks and etched away in the logic areas to form silicon nitride sidewalls on the gate electrode stacks in the logic areas. Thereafter, heavily doped source and drain regions are implanted in the logic areas. A second silicon nitride layer is deposited overlying the gate stacks and the silicon nitride sidewalls in the logic areas and overlying the first silicon nitride layer in the memory areas. The gate stacks are covered with a second oxide layer. Memory devices, such as polysilicon plugs and capacitors are formed in the memory areas. The second oxide layer and the memory devices are covered with a third oxide layer. Contact openings are simultaneously etched through the second and third oxide layers in both the logic areas and the memory areas wherein the etching has an etch stop at silicon nitride. The contact openings are filled with a first metal layer to complete fabrication of an integrated circuit device having logic and memory cells on a single semiconductor substrate.


REFERENCES:
patent: 5633188 (1997-05-01), Ogawa
patent: 5798289 (1998-08-01), Ajika et al.
patent: 5863820 (1999-01-01), Huang
patent: 5998251 (1999-12-01), Wu et al.
patent: 6004843 (1999-12-01), Huang
patent: 6069037 (2000-05-01), Liao
patent:

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