Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-11-09
2000-11-28
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438233, 438592, 438723, 438735, 438743, 438647, 438299, H01L 21336
Patent
active
061534854
ABSTRACT:
A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi.sub.2 is formed on S/D regions and TiSi.sub.2 or CoSi.sub.2 is formed on Poly electrodes (lines or gates) by etching back a sidewall spacer on the poly electrodes. The invention has two silicide steps. The TiSi.sub.2 is formed over the S/D regions while the gate electrode is protected by a silicon nitride Cap layer. Next, an ILD layer formed over the S/D regions. The interlevel dielectric (ILD) layer, cap layer and spacers on the sidewalls of the gate electrodes are etched back. The invention has two embodiments for the composition of the spacers. In a second silicide step, Titanium silicide (TiSi.sub.x or TiSi.sub.2) or Cobalt silicide (CoSi.sub.x or CoSi.sub.2) is formed on the top and sidewalls of the electrodes. A key feature of the invention is that the gate contact silicide is formed on the top and sidewalls of the electrodes.
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Pey Kin-Leong
Siah Soh-Yun
Booth Richard
Chartered Semiconductor Manufacturing Ltd.
Hack Jonathan
Pike Rosemary L. S.
Saile George O.
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