Sacrificial silicon sidewall for damascene gate formation

Details Sacrificial silicon sidewall for damascene gate formation Sacrificial silicon sidewall for damascene gate formation

1999-12-20

2001-07-10

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S595000

Reexamination Certificate

active

06258679

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of fabricating metal oxide semiconductor field effect transistors (MOSFETs), and more particular to a method for damascene gate formation wherein a sacrificial silicon sidewall is employed during the processing.
BACKGROUND OF THE INVENTION
In complementary metal oxide semiconductor (CMOS) processing, sub-0.05 &mgr;m field effect transistor (FET) devices must be fabricated using techniques in which the gate region is formed from an etch process that exhibits a high selectivity rate (>30:1) while maintaining vertical sidewalls. One problem with using conventional processing is that n
+
- and p
+
-polysilicon have different etch rates; this results in the requirement of pre-doped polysilicon gate etch with even higher selectivity to oxide.
To avoid the above problem with prior art fabrication processes, a damascene technique is employed in fabricating the gate region of the CMOS structure. In the formation of a gate region utilizing a prior art damascene technique, a trough (or gate hole) is defined in a stack which consists of various material layers, e.g., A, B, C, etc. The material layers of the stack used for defining the trough, for example, layer A, is removed by employing a damage free process to maintain substrate integrity. Following subsequent processing steps that result in the trough being filled with a gate conductor, e.g., polysilicon, the gate conductor is polished back so that the gate conductor is planar with the top of material layer A. As indicated above, material layer A must be removed from the structure. Typically, the removal of this material layer is carried out utilizing a chemical etchant which is highly selective in removing the material layer as compared to the surrounding and/or underlying layers of the structure.
During the process of this removal, some of the gate conductor may be consumed. The consumption of some of the gate conductor during damascene etch back may effect the performance of the final device. An example of this is when material layer A of the stack is Si
3
N
4
and the removal process is carried out with a hot phosphoric acid wet etch. If the gate conductor is polysilicon that has various dopants embedded therein, the isotropic etch of the polysilicon could proceed at between 1/30 to 1/60 the rate of the nitride removal. The isotropic nature of such an etch would result in thickness and line width variances of the resulting conductive lines.
In view of the above-mentioned drawback with prior art damascene gate formation processes, there is a continued need for developing a new and improved damascene gate formation process wherein the material layers used in defining the gate region can be removed without adversely the gate conductor and/or the device performance properties of the resulting structure.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating MOSFETs utilizing a damascene gate formation process in which the material layers of the gate stack, i.e., the material layers used in defining the trough, can be removed without damaging the gate conductor that is formed in the trough. This objective is achieved in the present invention by forming a silicon sidewall on vertical surfaces of a trough formed in a gate stack and thereafter oxidizing the silicon sidewalls. The oxidized silicon protects the sidewalls of the gate conductor during the removal of the various material layers of the gate stack.
The method of the present invention is particularly useful in fabricating a sub-0.05 &mgr;m MOSFET.
Specifically, the method of the present invention comprises the steps of:
(a) forming a gate stack on a surface of a silicon-containing substrate, said gate stack having at least a pad oxide layer formed on said surface of said silicon-containing substrate and a nitride layer formed on said pad oxide layer;
(b) forming a trough in said gate stack stopping on said pad oxide layer exposing a portion of said pad oxide layer, said trough having vertical sidewalls;
(c) forming a conformal silicon layer on said gate stack and in said trough, including said vertical sidewalls and said exposed pad oxide layer;
(d) removing the conformal silicon layer from said gate stack and said exposed pad oxide layer whereby silicon remains on the vertical sidewalls of said trough;
(e) removing the exposed pad oxide layer from said trough exposing a portion of the silicon-containing substrate;
(f) oxidizing the silicon on said vertical sidewalls of the trough and in said exposed silicon-containing substrate forming oxide layers in said vertical sidewalls and on said exposed silicon-containing substrate;
(g) forming doped polysilicon in said trough;
(h) performing a second oxidation step in which an oxide layer is formed on a top surface of said doped polysilicon;
(i) removing the remaining nitride layer of the gate stack forming a gate region which is protected on all sides by oxides; and
(j) forming source and drain regions in said silicon-containing substrate.
In the above method, the silicon employed in step (c) may be undoped or doped. In a preferred embodiment of the present invention, the silicon is heavily doped utilizing conventional techniques well known in the art, i.e., ion implantation and activation anneal or by a conventional deposition process wherein doping is conducted in-situ. Doped silicon is preferred over undoped silicon in the present invention since the remaining doped material after oxidation is easy to etch using standard chemical etchants such as hot phosphoric acid. The term “heavily doped” is used in the present invention to denote a dopant concentration of about 10
18
atoms/cm
2
or above.


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