Salicide integration process for embedded DRAM devices

Details Salicide integration process for embedded DRAM devices Salicide integration process for embedded DRAM devices

1999-06-10

2000-09-12

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 218242

Patent

active

061177237

ABSTRACT:
A process for integrating the fabrication of DRAM devices, with NFET, and PFET logic devices, on the same semiconductor chip, has been developed. The process features the simultaneous formation of metal silicide layers, on the top surfaces of the NFET and PFET, polysilicon gate structures, as well as on the top surface of an N type doped, polysilicon layer, to be used for subsequent formation of the DRAM polysilicon gate structures. The formation of metal silicide layer also is realized on the heavily doped source/drain regions, of the NFET and PFET logic devices, but is intentionally prevented on the DRAM source/drain regions, to minimize junction leakage. In addition, this integrated fabrication process, allows the doping of the DRAM polysilicon gate structure to be accomplished without an additional photolithographic masking step.

REFERENCES:
patent: 5134085 (1992-07-01), Gilgen
patent: 5702988 (1997-12-01), Liang
patent: 5858831 (1999-01-01), Sung
patent: 5863820 (1999-01-01), Huang
patent: 5866451 (1999-02-01), Yoo et al.
patent: 5879986 (1999-03-01), Sung

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