Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-10-01
2003-05-20
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S276000, C438S279000, C438S587000
Reexamination Certificate
active
06566194
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to fabricating nonvolatile semiconductor memory devices. In particular, the present invention relates to improved methods of fabricating flash memory devices with bit lines that can serve as sources and/or drains.
BACKGROUND
A desire for compact size and high access speed has driven the development of EEPROM (electrically erasable programmable read only memory) flash memory devices. One such development, applicable to both conventional and SONOS (silicon-oxide-nitride-oxide-silicon) flash memory devices, provides a virtual ground array structure. While a non-virtual ground array structure has dedicated source and drain regions for reading and writing operations, a virtual ground array structure reduces the spacing between gates by employing bit lines that can serve as either sources or drains according to the voltages applied.
Reducing the size of flash memory devices increases their speed, but speed can be enhanced in other ways. In a large array, speed is enhanced by reducing the spacing between contacts along bit lines. Contacts take up room and generally require a broader spacing between adjacent word lines wherever the contacts are to be placed. A compromise between the gains of more narrowly spaced contacts and the cost of having more contacts is to place contacts along the bit lines at every 16 word lines.
The response delay associated with polysilicon word lines can be reduced by siliciding, which provides lower electrical resistance. Siliciding is generally carried out without masking in what is referred to as a self-aligned siliciding process (saliciding). Unfortunately, saliciding has proven difficult in virtual ground arrays. The saliciding process has a tendency to cause shorting between bit lines, particularly in the absence of oxide island isolation regions.
In general, memory devices are faster and more compact than ever. However, there remains a demand for ever faster and/or more compact memory devices.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some of its aspects. This summary is not an extensive overview of the invention and is intended neither to identify key or critical elements of the invention nor to delineate its scope. The primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides processes for doping and saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, word lines are doped prior to patterning the poly layer from which the word lines are formed in the core region. Thereby, the poly layer protects the substrate between the word lines from doping that could cause shorting between bit lines. The core can be masked during subsequent doping steps that take place after patterning the poly layer in the core region.
According to another aspect of the invention, immediately prior to saliciding, word lines are exposed while spacer material, dielectric, or like material protects the substrate between word lines. The spacer material or dielectric prevents the substrate from becoming salicided in a manner that, like doping, could cause shorting between bit lines.
The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
Other advantages and novel features of the invention will become apparent from the following detailed description of the invention and the accompanying drawings. The detailed description and drawings provide certain illustrative examples of the invention. These examples are indicative of but a few of the various ways in which the principles of the invention can be employed.
REFERENCES:
patent: 4173766 (1979-11-01), Hayes
patent: 5168334 (1992-12-01), Mitchell et al.
patent: 5284784 (1994-02-01), Manley
patent: 5349221 (1994-09-01), Shimoji
patent: 5717635 (1998-02-01), Akatsu
patent: 5768192 (1998-06-01), Eitan
patent: 5907171 (1999-05-01), Santin et al.
patent: 5966603 (1999-10-01), Eitan
patent: 5972751 (1999-10-01), Ramsbey et al.
patent: 6001689 (1999-12-01), Van Buskirk et al.
patent: 6023085 (2000-02-01), Fang
patent: 6025267 (2000-02-01), Pey et al.
patent: 6030871 (2000-02-01), Eitan
patent: 6074915 (2000-06-01), Chen et al.
patent: 6130453 (2000-10-01), Mei et al.
patent: 6143608 (2000-11-01), He et al.
patent: 6153467 (2000-11-01), Wu
patent: 6153471 (2000-11-01), Lee et al.
patent: 6157575 (2000-12-01), Choi
patent: 6159795 (2000-12-01), Higashitani et al.
patent: 6207492 (2001-03-01), Tzeng et al.
patent: 6306713 (2001-10-01), Hu et al.
patent: 6372580 (2002-04-01), Shiau
“A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” T.Y. Chan, et al., IEEE Electron Device Letters, vol. EDL 8, No. 3, Mar. 1987.
“An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure,” Daniel C. Guterman, et al., IEEE Transactions on Electron Devices, vol. ED-26, No. 4, Apr. 1979.
“NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” Boaz Eitan, et al., IEEE Electron Device Letters, vol. 21, No. 11 Nov. 2000.
Chang Chi
Ramsbey Mark T.
Sun Yu
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Ho Hoai
Tran Long
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