Reduced mask count process for manufacture of mosgated device

Reduced mask process for manufacture of MOS gated devices using

Reduced masking step CMOS transistor formation using...

Reduced parasitic leakage in semiconductor devices

Reduced topography DRAM cell fabricated using a modified...

Reducing agent for high-K gate dielectric parasitic...

Reducing contamination in a process flow of forming a...

Reducing dopant losses during annealing processes

Reducing external resistance of a multi-gate device using...

Reducing gate CD bias in CMOS processing

Reducing gate dielectric material to form a metal gate...

Reducing leakage currents in memories with phase-change...

Reducing oxidation under a high K gate dielectric

Reducing photoresist layer degradation in plasma immersion...

Reducing poly-depletion through co-implanting carbon and...

Reducing reactions between polysilicon gate electrodes and...

Reducing secondary injection effects

Reducing the dielectric constant of a portion of a gate...

Reducing the formation of electrical leakage pathways during...

Reduction in well implant channeling and resulting latchup...