Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-03
2001-07-24
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S586000, C438S683000, C438S714000
Reexamination Certificate
active
06265252
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to electronic device manufacture, and more particularly, but not exclusively, relates to integrated circuit device manufacturing techniques that minimize electrical leakage caused by silicidation.
One common failure mechanism experienced during the manufacture of integrated circuit devices with planar insulated gate field effect transistors (IGFETs) is electrical bridging of an oxide spacer situated between the transistor gate and its corresponding source or drain. This type of defect often manifests itself as low resistance leakage that prevents proper operation of the affected IGFET. Typically, bridging of the oxide gate spacer occurs as an unintended consequence of the formation of silicide contact areas along silicon surfaces of the device.
Generally, silicide formation includes placing a metal blanket in contact with selected silicon surface regions, and then heating the device to cause a reaction between the silicon and metal. A silicide film results from this reaction along the regions of silicon/metal contact. During such silicidation processing, one possible side-effect is the occurrence of oxide-metal reactions along the oxide surface of a gate spacer. These reactions are thought to occasionally lead to the formation of a thin silicide film over the spacer, sometimes resulting in a low resistance pathway or electrical short between the gate and a source or drain region. Further, the silicide compound formed on a silicon region adjacent the spacer sometimes overflows causing a low resistance pathway or electrical short. This problem becomes even more troublesome as integrated circuit devices are scaled down to provide critical dimensions deep in the submicron range.
One way to address this problem is to reduce the thickness of the metal blanket placed in contact with the spacer. Unfortunately, an unacceptably high sheet resistance of desired silicide regions may result when the thickness of the metal blanket contacting silicon is correspondingly reduced. Thus, there is a demand for better techniques to manufacture electronic devices. These techniques preferably include the reduction of gate spacer bridging as an unwanted side-effect of silicide formation.
SUMMARY OF THE INVENTION
One form of the present invention includes providing an improved integrated circuit device. In this form, the device may include one or more components having specially shaped features.
A further form of the present invention includes an improved process for manufacturing electronic devices. Preferably, this process is applied to field effect transistors having gate spacers and silicide contact areas.
In another form, a process to preferentially reduce thickness of a layer along selected regions of an integrated circuit device workpiece is provided.
Yet another form of the present invention includes a technique to shape a spacer structure. This technique may include plasma etching of the spacer with a gas mixture that preferably comprises a predetermined amount of molecular oxygen.
Other forms of the present invention additionally or alternatively include providing an integrated circuit workpiece with a polysilicon transistor gate member extending from a substrate and forming a pair of spacers from an oxide of silicon on opposing sides of the gate member. A metal layer is deposited on the workpiece having a first minimum thickness on the gate member and a second minimum thickness on the spacers less than the first minimum thickness. The workpiece is heated to form a silicide region on the gate member. The first minimum thickness is selected to provide a target sheet resistance of the silicide region below a predetermined maximum and the second minimum thickness is selected to maintain silicide bridging of the spacers below a target level. The second minimum thickness is controlled relative to the first minimum thickness in accordance with a surface profile of each of the spacers defined during their formation. The surface profile has a progressively steeper slope from a rounded upper shoulder portion to a lower wall portion. The lower wall portion extends away from the substrate with a generally vertical slope.
In still other forms, the present invention includes providing an integrated circuit workpiece having a polysilicon transistor gate member extending from a generally planar substrate and forming a pair of spacers on opposite sides of the gate member. A metal layer is deposited on the workpiece and the workpiece is heated to form a number of silicide regions. Formation of the spacers includes plasma etching with a gas mixture. This gas mixture includes one or more fluorocarbon compounds contributing about 80-99% by volume to the mixture. Further, the mixture includes about 1-20% by volume oxygen. It has been found that this mixture may be utilized to provide a steeper spacer slope.
In still further forms of the present invention, an integrated circuit workpiece is provided that has a polysilicon transistor gate member extending from a generally planar substrate. A pair of spacers are formed on opposing sides of the gate member that are shaped during formation to define a spacer profile with a rounded upper shoulder portion downwardly curving toward a lower wall portion. The workpiece is blanketed with a metal layer that has a first minimum thickness on the gate member and a second minimum thickness on each of the spacers. The workpiece is annealed after blanketing to form a number of silicide regions. Formation of the spacers includes defining their surface profile with a slope along the lower wall portion selected to establish a ratio of the first minimum thickness to the second minimum thickness of at least about 2.5.
Further forms, objects, features, embodiments, advantages, benefits, and aspects of the present invention shall become apparent from the drawings and description contained herein.
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Quach T. N.
VLSI Technology Inc.
Woodard Emhardt Naughton Moriarty & McNett
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