Reducing dopant losses during annealing processes

Details Reducing dopant losses during annealing processes Reducing dopant losses during annealing processes

2003-03-31

2004-12-21

Flynn, Nathan J. (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S197000, C438S301000, C438S369000, C438S517000, C438S696000, C257S316000

Reexamination Certificate

active

06833292

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to annealing processes in semiconductor device fabrication, and, more particularly, to reducing dopant losses during annealing processes in semiconductor device fabrication.
BACKGROUND OF THE INVENTION
Integrated circuits include various semiconductor devices, such as transistors and capacitors, for example. During the fabrication of such semiconductor devices, particular regions may be implanted with a dopant, or “doped,” and annealed to activate the doped regions. For example, during fabrication of a transistor structure, a source, drain and gate poly region may be doped, and the transistor structure may subsequently be placed in a furnace for one or more annealing process, such as a source/drain anneal, in order to activate the source, drain and gate regions. In addition, fabrication may include one or more silicidation processes which may include a silicide annealing process.
However, during these annealing processes, a portion of the dopant may escape or diffuse away from the source, drain and gate regions toward adjacent regions of the transistor structure. Such dopant losses in the source, drain and gate regions of the transistor structure reduce the effectiveness of the resulting transistor, and may even cause the transistor to operate improperly, such as by failing to turn on or off as desired. Compensating for such dopant losses may require an increase in the amount of energy or implant dosage used to implant dopant into the doped regions, which places additional strain on the implanting equipment.
For example,
FIG. 1
illustrates an example prior art transistor structure
10
including dopant losses occurring during a source/drain anneal. Transistor structure
10
comprises an active source region
12
and an active drain region
14
formed in a substrate
16
, as well as a gate region
18
. Substrate
16
may be formed from silicon, gallium arsenide, or any other material suitable to form a transistor substrate.
A gate dielectric layer
30
may be formed partially or completely over or around gate
18
. As shown in
FIG. 1
, gate dielectric
30
may also extend over source region
12
and/or drain region
14
. Gate dielectric layer
30
may comprise silicon dioxide or any other material suitable for forming a gate dielectric layer.
Source and drain regions
12
and
14
are formed by implanting one or more dopants through dielectric layer
30
into a first and second region
20
and
22
, respectively, of substrate
16
using any suitable known doping method. Dielectric layer
30
may be at least partially or significantly removed or degraded due to various fabrication processes performed prior to the implanting of dopants to form source and drain regions
12
and
14
. In some situations, dielectric layer
30
may be completely removed or degraded prior to the dopant being implanted. In such situations, upper portions of first and second regions
20
and
22
may be damaged by the dopant implanting process.
A first and second moderately doped region (MDD)
24
and
26
may also be formed in substrate
16
adjacent source region
12
and drain region
14
, respectively. Moderately doped regions
24
and
26
may be formed by implanting a lower concentration of dopant (as compared with source and drain regions
12
and
14
) into substrate
16
using any suitable known doping method.
Gate
18
is formed adjacent substrate
16
between source and drain regions
12
and
14
. It should be noted that the term “adjacent” as used throughout this document includes immediately adjacent (or contacting), as well as proximate to. Thus, for example, as shown in
FIG. 1
, gate
18
may be adjacent to substrate
16
with a thin dielectric layer
30
disposed between gate
18
and substrate
16
, as discussed below.
Gate
18
may comprise one or more conductive materials suitable for use as a transistor gate, such as titanium, titanium nitride, tungsten, polysilicon, or amorphous silicon. In some embodiments, gate
18
is formed by implanting one or more dopants into a gate poly region
28
of transistor structure
10
using any suitable known doping method. Source and drain regions
12
and
14
and gate
18
may be doped using one or more of the same or different doping processes.
A first deposited oxide layer
32
may be formed adjacent a first side
34
and a second side
36
of gate
18
, and may extend over at least a portion of source region
12
, drain region
14
and/or moderately doped regions
24
and
26
. A nitride layer
38
may be formed adjacent first deposited oxide layer
32
on each of the first and second sides
34
and
36
of gate
18
. In addition, a second deposited oxide layer
40
may be formed over nitride layer
38
on each of the first and second sides
34
and
36
of gate
18
.
It should be understood that although transistor structure
10
as shown in
FIG. 1
includes various layers
30
,
32
,
38
and
40
, in alternative embodiments transistor structure
10
may include any suitable combination of similar and/or different layers.
As discussed above, source and drain regions
12
and
14
are formed by implanting a dopant (or a plurality of dopants) through dielectric layer
30
into first and second regions
20
and
22
of substrate
16
. The dopant in source and drain regions
12
is then “activated” in order to define an active source
42
and an active drain
44
of a transistor by performing a source/drain anneal, or heat treatment, on transistor structure
10
.
During the source/drain anneal, a portion of the dopant within source region
12
, drain region
14
and gate poly region
28
diffuses or escapes into adjacent or surrounding areas. For example, arrows
46
and
48
indicate dopant diffusing from source and drain regions
12
and
14
, respectively, through dielectric layer
30
during the source/drain anneal. Similarly, arrows
50
indicate dopant diffusing from gate poly region
28
through dielectric layer
30
during the source/drain anneal.
Dielectric layer
30
may be operable to prevent a portion of, or reduce the amount of, dopant loss from source region
12
, drain region
14
and gate poly region
28
during the source/drain anneal, depending on the thickness of dielectric layer
30
. However, in conventional and advanced fabrication processes, dielectric layer
30
may be relatively thin (such as less than 20 angstroms, for example) or nonexistent, and therefore unable to prevent a significant amount of the dopant loss from source region
12
, drain region
14
and gate poly region
28
.
In addition, dielectric layer
30
may vary in thickness across the area of dielectric layer
30
, as well as throughout the various steps or sub-processes of the fabrication process, and, as discussed above, may be partially or even completely removed or degraded due to various fabrication processes, all of which may allow relatively large amounts of dopant to diffuse away from all or portions of source region
12
, drain region
14
and gate poly region
28
during the source/drain anneal.
At some time subsequent to the source/drain anneal shown in
FIG. 1
, one or more silicide regions may be formed in transistor structure
10
, which formation includes a silicide anneal process, as discussed below regarding FIG.
2
.
FIG. 2
illustrates prior art transistor structure
10
including dopant losses occurring during a silicide anneal. After the source/drain anneal (discussed above with reference to
FIG. 1
) is performed, dielectric layer
30
is removed (assuming that at least a portion of dielectric layer
30
still remains). As shown in
FIG. 2
, a metal layer (such as a layer of titanium, cobalt, nickel, or platinum, or other suitable metal), or film,
60
is deposited adjacent transistor structure
10
, such as by using a sputtering process, for example. Transistor structure
10
is then heated using a thermal cycle, which may include one or more heating processes, during which metal layer
60
reacts with the silicon in active source
42
, active drain
44
and g

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