Patterning methodology for uniformity control

Details Patterning methodology for uniformity control Patterning methodology for uniformity control

2010-11-03

2011-11-08

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S618000

Reexamination Certificate

active

08053323

ABSTRACT:
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

REFERENCES:
patent: 5981368 (1999-11-01), Gardner et al.
patent: 6191044 (2001-02-01), Yu et al.
patent: 2003/0211684 (2003-11-01), Guo
patent: 2010/0108264 (2010-05-01), Delgadino et al.

Affiliated with

Also associated with

Rating

Patterning methodology for uniformity control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Patterning methodology for uniformity control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Patterning methodology for uniformity control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4300447