Patterning of doped poly-silicon gates

Details Patterning of doped poly-silicon gates Patterning of doped poly-silicon gates

2008-06-24

2008-06-24

Le, Thao X. (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000

Reexamination Certificate

active

07390708

ABSTRACT:
A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.

REFERENCES:
patent: 6682999 (2004-01-01), Mucha
patent: 2006/0163665 (2006-07-01), Chuang et al.
patent: 2007/0004224 (2007-01-01), Currie
patent: 2007/0010037 (2007-01-01), Li et al.
patent: 2007/0057335 (2007-03-01), Tsuchiya et al.
patent: 2007/0099385 (2007-05-01), Nakajima et al.
patent: 20070161952 (2007-06-01), None

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