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Memory cell having bar-shaped storage node contact plugs and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell having implanted region formed between select and se

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell of the EEPROM type having its threshold adjusted...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell of the EEPROM type having its threshold set by...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell structure for semiconductor memory device and fabric

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell structure integrating self aligned contact...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell that includes a vertical transistor and a trench cap

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell that includes a vertical transistor and a trench cap

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell that includes a vertical transistor and a trench...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell with an asymmetric crystalline structure

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell with plasma-grown oxide spacer for reduced DIBL...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell with reduced size and standby current

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell with transfer device node in selective polysilicon

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell with vertical transistor and buried word and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cell, memory device and method of fabricating the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cells with vertical transistor and capacitor and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory cells, methods of forming dielectric materials, and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory circuitry and method of forming memory circuitry

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Memory device and fabrication method thereof

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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