Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-18
2001-03-13
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S386000
Reexamination Certificate
active
06200851
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a memory cell, and more particularly, to a memory cell useful in a dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
A DRAM generally includes a two-dimensional array of rows and columns of memory cells integrated in a semiconductive chip. A popularly used memory cell with n-channel metal-oxide-silicon (MOS) DRAMs is the “switched capacitor” memory cell which has a n-channel MOS transistor (also denoted as a pass transistor) and a capacitor (also denoted as a storage device). One output terminal of the transistor is coupled to a first terminal (storage plate) of the capacitor and the second terminal (reference plate) of the capacitor is typically coupled to a fixed voltage source. The gates of all of the transistors of a common row of memory cells are coupled to a common word line and the second output terminals of the pass transistors of a column of memory cells are all coupled to a common separate bit line. In a n-channel MOS transistor positive current is defined as flowing along the channel from the drain to the source output terminals. During operation of the switched capacitor memory cell current reverses through the transistor and thus the drain and source reverse. For the sake of discussion herein the first output terminal of the pass transistor shall be denoted as the source and the second output terminal shall be denoted as the drain.
In its early form, both the channel of the pass transistor and the storage surface of the capacitor extended largely horizontally along the active surface area of the chip. This latter characteristic was found to limit the density with which the memory cells could be packed in a single chip because, to achieve the desired amount of capacitance necessary for reliability, it was important to use considerable active surface area for the capacitor.
To meet this problem, it has become the practice to employ in high density DRAMs a memory cell that uses a capacitor whose storage surface extends essentially perpendicular to the active surface area, typically in a trough (trench) that extends vertically in the chip so that the capacitance can be increased as needed, simply by extending the depth of the trench with little effect on the chip surface area consumed by the capacitor.
In U.S. Pat. No. 5,376,575, which issued on Dec. 27, 1994, there is proposed a DRAM that reverses this approach and employs a storage capacitor at the active surface of the chip whose storage surface extends parallel to the active surface and a buried pass transistor that underlies the storage capacitor and whose channel extends vertically in a trench that extends vertically from the active surface. This design permits the bit line that normally extends over the active surface of the chip to be buried in the interior of the chip, thereby saving the area of the active surface of the chip formerly occupied by the bit line. Additionally, the vertical orientation of the transistor permits the length of the channel of the transistor to be increased, as needed, to avoid undesirable short-channel effects that generally limit how much the channel length can be effectively shortened. However, the burial of the bit lines can complicate the fabrication process, particularly in dense arrays where each bit line needs to serve all the cells in a column. Presently there is known no report in the literature of a memory cell of this kind, but its manufacture would appear to be difficult for use in state of the art DRAMs.
Another problem that arises with increasing the density of memory cells in an array is the increasing difficulty in achieving consistently the alignment required of the various processes involved in the commercial manufacture of such arrays.
It is desirable to have a switched capacitor memory cell that requires relatively little semiconductor surface area, has adequate capacitance, and can be fabricated relatively easily.
SUMMARY OF THE INVENTION
The present invention relates to a novel memory cell structure and a process to fabricate such structure. The structure facilitates the simplification of processes in the fabrication of high density DRAMs.
An illustrative embodiment of the invention is embodied in a chip that comprises a silicon body. Typically the silicon body may have been cut from a monocrystalline silicon wafer or been formed as an epitaxial layer grown either on a silicon layer or an insulating substrate, such as sapphire. The invention permits the more critical steps of the processing, such as those involving minimum area lithography to be done advantageously early in the processing where better planarity is available. Additionally, invention permits the increased use of self-alignment processes that simplify achieving the close alignment required in the manufacture of high-density DRAMs.
One embodiment of the invention comprises a memory cell that uses a vertical trench in which a lower portion helps form a vertical capacitor and an upper portion helps form a vertical transistor. The memory cell is formed in a chip that includes a silicon substrate, which for example is monocrystalline in structure. The silicon substrate comprises a polysilicon-filled vertical trench and a pass transistor comprising a source, drain, channel, and gate. The source, drain, and channel are formed in an upper portion of the monocrystalline substrate and the gate is formed in an upper portion of the polysilicon-filled trench with the gate dielectric as a layer of oxide along an upper sidewall portion of the trench. The storage capacitor of the memory cell has a storage plate in a lower portion of the polysilicon-filled trench, a reference plate in a lower portion of the monocrystalline substrate, and a dielectric layer along a lower wall portion of the trench.
In an alternative embodiment, the pass transistor is largely located in the monocrystalline substrate in a shallow region (well) of one conductivity type and the storage capacitor is largely located in the monocrystalline substrate in a deeper region (well) of the opposite conductivity type. Additionally, the active area of each memory cell at the surface of the chip is defined by a shallow isolation trench filled with dielectric, typically silicon oxide.
In another embodiment, the transistor and capacitor are formed in a chip that comprises a silicon body comprising a monocrystalline substrate and a vertical polysilicon-filled trench. The transistor has a source and drain vertically spaced-apart along a channel extending in the body along a sidewall portion of the polysilicon-filled trench, and a gate located in the polysilicon fill and has gate dielectric which lies along the sidewall portion of the polysilicon-filled trench. The capacitor has a storage plate in the polysilicon fill, a reference plate in the monocrystalline substrate, and a dielectric layer on a wall portion of the polysilicon-filled trench between the reference plate and the storage plate. The transistor is located above the capacitor in the silicon body.
In still another embodiment, the invention comprises a memory cell having a capacitor and a n-channel field effect transistor having a drain, a source, and a gate. The memory cell is formed in a silicon chip that comprises a silicon body having a major surface and comprising a monocrystalline substrate and a vertical polysilicon-filled trench. The transistor has the source and drain thereof spaced apart vertically in the body along a channel extending in the substrate along a sidewall portion of the polysilicon-filled trench, the gate in the polycrystalline-filled trench, and the gate dielectric along the sidewall portion of the polysilicon-filled trench. The capacitor has a storage plate in the polysilicon-filled trench, a reference plate in the monocrystalline substrate, and a dielectric thereof in an insulating layer on a sidewall portion of the polysilicon-filled trench between said reference plate and said storage plate. The transistor is located above the capacitor in the silicon body and has a portion thereof that is on
Braden Stanton
Hoang Quoc
Nelms David
Siemens Aktiengesellschaft
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